Fair dynamic arbitration for a multiprocessor communications bus
Abstract
The finite element machine (FEM) is an experimental parallel computer consisting of an array of 36 asynchronous microcomputers. One method of interprocessor communication of FEM is a bi-directional parallel bus which uses a dynamic arbitration scheme to increase bus bandwidth. Testing of this bus revealed an imbalance in transfer rates for individual processors. The imbalance was traced to a defect in arbiter design, and two criteria were identified which must be met to ensure fair dynamic arbitration. These involve (1) priority sequencing, and (2) the efficiency of the arbiter. 3 references.
- Authors:
- Publication Date:
- Research Org.:
- Kentron International Inc., Hampton, VA
- OSTI Identifier:
- 5001010
- Resource Type:
- Journal Article
- Journal Name:
- Comput. Archit. News; (United States)
- Additional Journal Information:
- Journal Volume: 5
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; EQUIPMENT INTERFACES; COMMUNICATIONS; EXECUTIVE CODES; MICROPROCESSORS; PARALLEL PROCESSING; COMPUTER CODES; COMPUTERS; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; PROGRAMMING; 990200* - Mathematics & Computers
Citation Formats
Knott, J D, and Crockett, T W. Fair dynamic arbitration for a multiprocessor communications bus. United States: N. p., 1982.
Web. doi:10.1145/641559.641560.
Knott, J D, & Crockett, T W. Fair dynamic arbitration for a multiprocessor communications bus. United States. https://doi.org/10.1145/641559.641560
Knott, J D, and Crockett, T W. 1982.
"Fair dynamic arbitration for a multiprocessor communications bus". United States. https://doi.org/10.1145/641559.641560.
@article{osti_5001010,
title = {Fair dynamic arbitration for a multiprocessor communications bus},
author = {Knott, J D and Crockett, T W},
abstractNote = {The finite element machine (FEM) is an experimental parallel computer consisting of an array of 36 asynchronous microcomputers. One method of interprocessor communication of FEM is a bi-directional parallel bus which uses a dynamic arbitration scheme to increase bus bandwidth. Testing of this bus revealed an imbalance in transfer rates for individual processors. The imbalance was traced to a defect in arbiter design, and two criteria were identified which must be met to ensure fair dynamic arbitration. These involve (1) priority sequencing, and (2) the efficiency of the arbiter. 3 references.},
doi = {10.1145/641559.641560},
url = {https://www.osti.gov/biblio/5001010},
journal = {Comput. Archit. News; (United States)},
number = ,
volume = 5,
place = {United States},
year = {Wed Sep 01 00:00:00 EDT 1982},
month = {Wed Sep 01 00:00:00 EDT 1982}
}
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