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Title: 3D packaging for integrated circuit systems

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.
Authors:
;  [1]
  1. eds.
Publication Date:
OSTI Identifier:
420397
Report Number(s):
SAND--96-2801
ON: DE97001854; TRN: 97:000748
DOE Contract Number:
AC04-94AL85000
Resource Type:
Technical Report
Resource Relation:
Other Information: PBD: Nov 1996
Research Org:
Sandia National Labs., Albuquerque, NM (United States)
Sponsoring Org:
USDOE, Washington, DC (United States)
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; 36 MATERIALS SCIENCE; INTEGRATED CIRCUITS; PACKAGING; MICROELECTRONICS; THERMAL ANALYSIS; SILICON; MASKING; EPOXIDES