Breakdown voltage improvement of standard MOS technologies targeted at smart power

Conference · Sun Dec 31 00:00:00 EST 1995

OSTI ID:415488

Santos, P M; Simas, M I.C.; Lanca, M ^[1]; Finco, S; Behrens, F H ^[2]

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1. Inst. Superior Tecnico-CEAUTL, Lisboa (Portugal)
2. Fundacao Centro Technologico para Informatica, Campinas, Sao Paulo (Brazil)

This paper presents and discusses trade-offs of three different design techniques intended to improve the breakdown voltage of n-type lateral medium power transistors to be fabricated in a conventional low cost CMOS technology. A thorough analysis of the static and dynamic characteristics of the modified structures was carried out with the support of a two-dimensional device simulator. The motivation behind this work was the construction of a low cost smart power microsystem, including control, sensing and protection circuitries, targeted at an electronic ballast for efficient control of the power delivered to fluorescent lamps.

• OSTI ID: 415488
• Report Number(s): CONF-9510203-; TRN: IM9704%%119
• Resource Relation: Conference: IEEE/Industrial Application Society conference, Orlando, FL (United States), 8-12 Oct 1995; Other Information: PBD: 1995; Related Information: Is Part Of Conference record of the 1995 IEEE Industry Applications Society thirtieth IAS annual meeting. Volume 2; PB: 954 p.
• Country of Publication: United States
• Language: English

Related Subjects

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATION
LIGHTING SYSTEMS
BALLASTS
CONTROL
ENERGY EFFICIENCY
POWER SUPPLIES
POWER CONDITIONING CIRCUITS