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Title: Scalable and thermally robust perpendicular magnetic tunnel junctions for STT-MRAM

Thermal budget, stack thickness, and dipolar offset field control are crucial for seamless integration of perpendicular magnetic junctions (pMTJ) into semiconductor integrated circuits to build scalable spin-transfer-torque magnetoresistive random access memory. This paper is concerned with materials and process tuning to deliver thermally robust (400 °C, 30 min) and thin (i.e., fewer layers and integration-friendly) pMTJ utilizing Co/Pt-based bottom pinned layers. Interlayer roughness control is identified as a key enabler to achieve high thermal budgets. The dipolar offset fields of the developed film stacks at scaled dimensions are evaluated by micromagnetic simulations. This paper shows a path towards achieving sub-15 nm-thick pMTJ with tunneling magnetoresistance ratio higher than 150% after 30 min of thermal excursion at 400 °C.
Authors:
 [1] ; ; ; ; ;  [2]
  1. QUALCOMM Europe Incorporated, Kapeldreef 75, 3001 Heverlee (Belgium)
  2. Corporate Research and Development, Qualcomm Technologies Incorporated, San Diego, California 92121-1714 (United States)
Publication Date:
OSTI Identifier:
22415150
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 106; Journal Issue: 3; Other Information: (c) 2015 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; COBALT; INTEGRATED CIRCUITS; LAYERS; MAGNETORESISTANCE; PLATINUM; SEMICONDUCTOR MATERIALS; SIMULATION; SPIN; SUPERCONDUCTING JUNCTIONS; TEMPERATURE RANGE 0400-1000 K; TUNNEL EFFECT