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Title: The fundamental downscaling limit of field effect transistors

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.
Authors:
;  [1]
  1. Sandia National Laboratories, Albuquerque, New Mexico 87185-1322 (United States)
Publication Date:
OSTI Identifier:
22399060
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 106; Journal Issue: 19; Other Information: (c) 2015 Author(s); Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; COMPUTERIZED SIMULATION; DENSITY; ERRORS; MOSFET; OPERATION; ORIENTATION; PERFORMANCE; QUANTUM MECHANICS; SILICON; TEMPERATURE RANGE 0273-0400 K