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Title: Stress management for 3D through-silicon-via stacking technologies - The next frontier -

The status of the development of a Design-for-Stress simulation flow that captures the stress effects in packaged 3D-stacked Si products like integrated circuits (ICs) using advanced via-middle Through Si Via technology is outlined. The next set of challenges required to proliferate the methodology and to deploy it for making and dispositioning real Si product decisions are described here. These include the adoption and support of a Process Design Kit (PDK) that includes the relevant material properties, the development of stress simulation methodologies that operate at higher levels of abstraction in a design flow, and the development and adoption of suitable models required to make real product reliability decisions.
Authors:
; ;  [1]
  1. Qualcomm Inc., San Diego, CA (United States)
Publication Date:
OSTI Identifier:
22311264
Resource Type:
Journal Article
Resource Relation:
Journal Name: AIP Conference Proceedings; Journal Volume: 1601; Journal Issue: 1; Conference: International conference on stress induced phenomena and reliability in 3D microelectronics, Kyoto (Japan), 28-30 May 2012; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; DESIGN; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; RELIABILITY; SILICON; STRESSES; THREE-DIMENSIONAL CALCULATIONS