skip to main content

SciTech ConnectSciTech Connect

Title: Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.
Authors:
; ; ; ; ; ; ; ;  [1] ;  [2] ; ; ; ; ; ;  [3]
  1. IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland)
  2. CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France)
  3. IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)
Publication Date:
OSTI Identifier:
22303557
Resource Type:
Journal Article
Resource Relation:
Journal Name: APL Materials; Journal Volume: 2; Journal Issue: 8; Other Information: (c) 2014 Author(s); Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; CURIUM OXIDES; DISLOCATIONS; ELECTRON MOBILITY; GALLIUM ARSENIDES; INDIUM ARSENIDES; MECHANICAL POLISHING; MOS TRANSISTORS; SUBSTRATES