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Title: GaAs buffer layer technique for vertical nanowire growth on Si substrate

Gold catalyzed vapor-liquid-solid method is widely applied to III–V nanowire (NW) growth on Si substrate. However, the easy oxidation of Si, possible Si contamination in the NWs, high defect density in the NWs, and high sensitivity of the NW morphology to growth conditions largely limit its controllability. In this work, we developed a buffer layer technique by introducing a GaAs thin film with predefined polarity as a template. It is found that samples grown on these buffer layers all have high vertical NW yields in general, due to the single-orientation of the buffer layers. Low temperature buffer with smoother surface leads to highest yield of vertical NWs, while high temperature (HT) buffer with better crystallinity results in perfect NW quality. The defect-free property we observed here is very promising for optoelectronic device applications based on GaAs NW. Moreover, the buffer layers can eliminate Si contamination by preventing Si-Au alloy formation and by increasing the thickness of the Si diffusion barrier, thus providing more flexibility to vertical NW growth. The buffer layer technique we demonstrated here could be easily extended to other III-V on Si system for electronic and photonic applications.
Authors:
; ; ; ;  [1] ;  [2]
  1. Department of Electrical Engineering, Stanford University, Stanford, California 94305 (United States)
  2. Department of Materials Science, University of Science and Technology Beijing, Beijing 100083 (China)
Publication Date:
OSTI Identifier:
22293061
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 104; Journal Issue: 8; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; BUFFERS; CRYSTAL DEFECTS; CRYSTAL GROWTH; DIFFUSION BARRIERS; GALLIUM ARSENIDES; GOLD; GOLD ALLOYS; NANOSTRUCTURES; SILICON; SILICON ALLOYS; SUBSTRATES; TEMPERATURE RANGE 0065-0273 K; TEMPERATURE RANGE 0400-1000 K; THICKNESS; THIN FILMS