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Title: Characterization of vertical strain silicon MOSFET incorporating dielectric pocket (SDP-VMOSFET)

The vertical Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) leads to a double channel width that can increase the packaging density. The strained silicon MOSFET was introduced to modify the carrier transport properties of silicon in order to enhance transport of both electrons and holes within strained layer. Dielectric pocket was act to control encroachment of the drain doping into the channel and reduce short channel effects (SCE). SDP-VMOSFET which was a combination of those advantages was proposed to overcome the SCE in term of leakage current, threshold voltage roll-off also Drain Induce Barrier Lowering (DIBL). As a result, SDP-VMOSFET produces a better threshold voltage and DIBL compared to related structures. Meanwhile, it gives slightly increased for leakage current compared to Vertical MOSFET Incorporating Dielectric Pocket. The characteristics of the SDP-VMOSFET are analyzed in order to optimize the performance of the device and leading to the next generation of IC technology.
Authors:
; ; ; ; ; ;  [1]
  1. Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka (Malaysia)
Publication Date:
OSTI Identifier:
22266022
Resource Type:
Journal Article
Resource Relation:
Journal Name: AIP Conference Proceedings; Journal Volume: 1586; Journal Issue: 1; Conference: NNS2013: 5. nanoscience and nanotechnology symposium, Surabaya (Indonesia), 23-25 Oct 2013; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; DENSITY; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; LEAKAGE CURRENT; MOSFET; SEMICONDUCTOR MATERIALS; SILICON; STRAINS