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Title: Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.
Authors:
;  [1] ;  [2]
  1. Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d'Ascq (France)
  2. Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)
Publication Date:
OSTI Identifier:
22253214
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 103; Journal Issue: 26; Other Information: (c) 2013 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
77 NANOSCIENCE AND NANOTECHNOLOGY; ELECTRIC POTENTIAL; LAYERS; LENGTH; NOISE; QUANTUM WIRES; SILICON; TRANSISTORS