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Title: Schottky barrier height reduction for metal/n-InP by inserting ultra-thin atomic layer deposited high-k dielectrics

Fermi level pinning at metal/n-InP interface and effective Schottky barrier height (Φ{sub B,eff}) were optimized by inserting ultrathin dielectrics in this work. Comparing the inserted monolayer and bilayer high-k dielectrics, we demonstrated that the introduction of bilayer dielectrics can further reduce Φ{sub B,eff} (from 0.49 eV to 0.22 eV) than the monolayer dielectric (from 0.49 eV to 0.32 eV) even though the overall dielectric thickness was thicker. The additional dipole formed at high-k/high-k interfaces could be used to expound the mechanism. This work proposed an effective solution to reduce resistance contacts for InP based transistors and Schottky barrier transistors.
Authors:
; ; ; ; ;  [1] ; ;  [2]
  1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433 (China)
  2. Department of Materials Science, Fudan University, Shanghai 200433 (China)
Publication Date:
OSTI Identifier:
22253205
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 103; Journal Issue: 26; Other Information: (c) 2013 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; DEPOSITION; DIELECTRIC MATERIALS; FERMI LEVEL; INDIUM PHOSPHIDES; LAYERS; TRANSISTORS