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Title: Multiple core computer processor with globally-accessible local memories

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
Authors:
; ;
Publication Date:
OSTI Identifier:
1325760
Report Number(s):
9,448,940
14/354,257
DOE Contract Number:
AC02-05CH11231
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012 Oct 26
Research Org:
Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING