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Title: Multiple core computer processor with globally-accessible local memories

Patent ·
OSTI ID:1325760
; ;

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

Research Organization:
Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC02-05CH11231
Assignee:
The Regents of the University of California (Oakland, CA)
Patent Number(s):
9,448,940
Application Number:
14/354,257
OSTI ID:
1325760
Resource Relation:
Patent File Date: 2012 Oct 26
Country of Publication:
United States
Language:
English

References (14)

Managing cache memory in a parallel processing environment patent February 2011
Processor memory system patent February 2011
Distributed home-node hub patent April 2013
Near neighbor data cache sharing patent May 2014
Systems and methods for a fast interconnect table patent December 2014
Multi-core processor system, cache coherency control method, and computer product patent March 2015
Shared load-store unit to monitor network activity and external memory transaction status for thread switching patent May 2015
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes patent-application March 2005
Protocol for maintaining cache coherency in a CMP patent-application June 2005
Processor Memory System patent-application June 2009
eXtreme Virtual Memory patent-application December 2009
Systems And Methods For Managing Large Cache Services In A Multi-Core System patent-application June 2011
Advanced Processor With Mechanism For Fast Packet Queuing Operations patent-application October 2011
Execution Migration patent-application October 2011

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