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Title: OpenSoC Fabric

Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric2 infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible.
Publication Date:
OSTI Identifier:
1323923
Report Number(s):
OPENSOCFABRIC; 003074MLTPL00
R&D Project: KRD1221; 2014-154
DOE Contract Number:
AC02-05CH11231
Software Revision:
00
Software Package Number:
003074
Software Package Contents:
ALL DISTRIBUTIION WILL BE HANDLED BY LAWRENCE BERKELEY NATIONAL LABORATORY.
Software CPU:
MLTPL
Open Source:
Yes
Copyrighted
Source Code Available:
Yes
Research Org:
Lawrence Berkeley National Laboratory
Sponsoring Org:
United States Department of Energy
Contributing Orgs:
Farzad Fatollahi-Fard, David Donofrio, Georgios Michelgiannakis, John Bachan
Country of Publication:
United States

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