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Title: SMT-Aware Instantaneous Footprint Optimization

Modern architectures employ simultaneous multithreading (SMT) to increase thread-level parallelism. SMT threads share many functional units and the whole memory hierarchy of a physical core. Without a careful code design, SMT threads can easily contend with each other for these shared resources, causing severe performance degradation. Minimizing SMT thread contention for HPC applications running on dedicated platforms is very challenging, because they usually spawn threads within Single Program Multiple Data (SPMD) models. To address this important issue, we introduce a simple scheme for SMT-aware code optimization, which aims to reduce the memory contention across SMT threads.
Authors:
; ;
Publication Date:
OSTI Identifier:
1322525
Report Number(s):
PNNL-SA-117062
KJ0402000
DOE Contract Number:
AC05-76RL01830
Resource Type:
Conference
Resource Relation:
Conference: Proceedings of the 25th ACM international Symposium on High-Performance and Distributed Computing (HPDC 2016), May 31-June 4, 2016, Kyoto, Japan, 267-279
Publisher:
ACM, NEW YORK, New York
Research Org:
Pacific Northwest National Laboratory (PNNL), Richland, WA (US)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
SMT; Memory Hierarchy; Instantaneous Footprint; SMTAware Optimization; Locality; Performance Tools