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Title: Tag-Split Cache for Efficient GPGPU Cache Utilization

Modern GPUs employ cache to improve memory system efficiency. However, large amount of cache space is underutilized due to irregular memory accesses and poor spatial locality which exhibited commonly in GPU applications. Our experiments show that using smaller cache lines could improve cache space utilization, but it also frequently suffers from significant performance loss by introducing large amount of extra cache requests. In this work, we propose a novel cache design named tag-split cache (TSC) that enables fine-grained cache storage to address the problem of cache space underutilization while keeping memory request number unchanged. TSC divides tag into two parts to reduce storage overhead, and it supports multiple cache line replacement in one cycle.
Authors:
; ; ;
Publication Date:
OSTI Identifier:
1322523
Report Number(s):
PNNL-SA-117315
453040135
DOE Contract Number:
AC05-76RL01830
Resource Type:
Conference
Resource Relation:
Conference: Proceedings of the International Conference on Supercomputing (ICS 2016), June 1-3, 2016, Istanbul, Turkey, Paper No. 43
Publisher:
ACM, New York, New York
Research Org:
Pacific Northwest National Laboratory (PNNL), Richland, WA (US)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
Throughput-oriented architecture design; performance and energy optimization