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Title: Testsofa Design Details and Theory of Operation

The Testsofa is used to explore the functioning of an integrated circuit. It characterizes pin functions via pin profiling, then serves as an interface to a Boss server which creates a finite state machine (FSM) model using branch exploration. This exploration is done via a stimulus/response process, which will be explained in the Internal Logic Testing section.
Authors:
 [1]
  1. Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
Publication Date:
OSTI Identifier:
1314416
Report Number(s):
PNNL--25318
830403000
DOE Contract Number:
AC05-76RL01830
Resource Type:
Technical Report
Research Org:
Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING integrated circuit; finite state machine; pin profiling