Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs

Journal Article · Thu Apr 21 00:00:00 EDT 2016 · IEEE Transactions on Components, Packaging, and Manufacturing Technology

DOI:https://doi.org/10.1109/TCPMT.2016.2541615· OSTI ID:1249073

Choi, Sukwon ^[1]; Peake, Gregory M. ^[2]; Keeler, Gordon A. ^[2]; Geib, Kent M. ^[2]; Briggs, Ronald D. ^[2]; Beechem, Thomas E. ^[2]; Shaffer, Ryan A. ^[2]; Clevenger, Jascinda ^[2]; Patrizi, Gary A. ^[2]; Klem, John F. ^[2]; Tauke-Pedretti, Anna ^[2]; Nordquist, Christopher D. ^[2]

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1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Pennsylvania State Univ., University Park, PA (United States)
2. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e., positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.

• Research Organization: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• Grant/Contract Number: AC04-94AL85000
• OSTI ID: 1249073
• Report Number(s): SAND-2016-1304J; 619378
• Journal Information: IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. PP, Issue 99; ISSN 2156-3950
• Publisher: IEEE
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
III-V semiconductor materials
heterojunction bipolar transistors (HBTs)
infrared (IR) imaging
integrated circuit technology
temperature measurement
thermal management of electronics
thermoreflectance imaging