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Title: Integrated circuit test-port architecture and method and apparatus of test-port generation

A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.
Authors:
Publication Date:
OSTI Identifier:
1246915
Report Number(s):
9,311,444
14/328,379
DOE Contract Number:
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 Jul 10
Research Org:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING