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Title: Single event upset protection circuit and method

An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates `odd` parity, and to pass the redundant data value to the output when the parity engine output indicates `even` parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.
Authors:
;
Publication Date:
OSTI Identifier:
1243318
Report Number(s):
9,292,378
14/290,648
DOE Contract Number:
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 May 29
Research Org:
Sandia National Laboratories (SNL-CA), Livermore, CA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING