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Title: Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Patent ·
OSTI ID:1243039
;

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
9,286,423
Application Number:
13/435,707
OSTI ID:
1243039
Resource Relation:
Patent File Date: 2012 Mar 30
Country of Publication:
United States
Language:
English

References (41)

SoC HW/SW verification and validation conference January 2011
A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM journal January 2006
Intel® atom™ processor core made FPGA-synthesizable conference January 2009
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation conference January 2012
Time multiplexed programmable logic device patent July 1997
Memory controller architecture patent September 2000
Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit patent February 2001
Method and apparatus for unified simulation patent January 2006
Apparatus and method for initializing an integrated circuit device and activating a function of the device once an input power supply has reached a threshold voltage patent December 2007
Processing system with interspersed stall propagating processors and communication elements patent August 2008
System and method of mapping memory blocks in a configurable integrated circuit patent September 2009
Sleep and stall in an in-circuit emulation system patent August 2010
Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor patent April 2011
Input/output multiplexer bus patent November 2011
System and method for providing compact mapping between dissimilar memory systems patent March 2012
Generating user clocks for a prototyping environment patent November 2013
Method and apparatus for test generation during circuit design patent-application June 2002
Method and System for Design Verification of Electronic Circuits patent-application August 2002
Media cross conversion interface patent-application March 2003
Hierarchical, network-based emulation system patent-application December 2004
Clock distribution in a circuit emulator patent-application June 2005
Method and apparatus for emulation of logic circuits patent-application July 2005
Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol patent-application November 2005
Automatic hidden refresh in a dram and method therefor patent-application December 2005
Method of programming a co-verification system patent-application January 2006
Behavior processor system and method patent-application June 2006
Method and circuit for rapid alignment of signals patent-application June 2008
Communication Scheme Between Programmable Sub-Cores in an Emulation Environment patent-application November 2008
Techniques For Use With Automated Circuit Design and Simulations patent-application December 2008
Method and Apparatus to Debug an Integrated Circuit Chip Via Synchronous Clock Stop and Scan patent-application January 2009
Simulation Apparatus and Control Method of Simulation patent-application March 2009
Clock generators for generation of in-phase and quadrature clock signals patent-application June 2009
Peak Power Detection in Digital Design Using Emulation Systems patent-application October 2009
FPGA Simulated Annealing Accelerator patent-application December 2009
Memory Controller Interface patent-application January 2010
Memory-Based Trigger Generation Scheme in an Emulation Environment patent-application September 2010
Control Board For Connection Between FPGA Boards And Test Device Thereof patent-application December 2011
Method and Infrastructure for Cycle-Reproducible Simulation on Large Scale Digital CIrcuits on a Coordinated Set of Field-Programmable Gate Arrays (FPGAs) patent-application May 2012
Logic Verification Module Apparatus to Serve as a Hyper Prototype for Debugging an Electronic Design that Exceeds the Capacity of a Single FPGA patent-application November 2012
Wire Like Link for Cycle Reproducible and Cycle Accurate Hardware Accelerator patent-application July 2013
Cycle Accurate and Cycle Reproducible Memory for an FPGA Based Hardware Accelerator patent-application December 2013

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