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Title: Combined group ECC protection and subgroup parity protection

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
Authors:
; ; ;
Publication Date:
OSTI Identifier:
1241521
Report Number(s):
9,252,814
13/918,127
DOE Contract Number:
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 Jun 14
Research Org:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; 99 GENERAL AND MISCELLANEOUS