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Title: Near memory data structure rearrangement

Conference ·
; ;

Research Organization:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
OSTI ID:
1236123
Report Number(s):
LLNL-PROC-675466
Resource Relation:
Conference: Presented at: Memsys, Alexandria, VA, United States, Oct 06 - Oct 08, 2015
Country of Publication:
United States
Language:
English

References (8)

A low cost, multithreaded processing-in-memory system
  • Brockman, Jay B.; Thoziyoor, Shyamkumar; Kuntz, Shannon K.
  • Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04 https://doi.org/10.1145/1054943.1054946
conference January 2004
Data reorganization engines for the next generation of system-on-a-chip FPGAs conference January 2002
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System journal May 2005
Programming the FlexRAM parallel intelligent memory system
  • Fraguela, Basilio B.; Renau, Jose; Feautrier, Paul
  • Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03 https://doi.org/10.1145/781498.781505
conference January 2003
Processing in memory: the Terasys massively parallel PIM array journal April 1995
In-Memory Data Rearrangement for Irregular, Data-Intensive Computing journal August 2015
Active Memory Cube: A processing-in-memory architecture for exascale systems journal March 2015
A Logic-in-Memory Computer journal January 1970

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Related Subjects

97 MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE