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Title: Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS Technologies for High-Energy Physics Experiments

The Long Baseline Neutrino Facility intends to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This, then, requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are investigated. Our results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.
 [1] ;  [1] ;  [2] ;  [2]
  1. Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
  2. Southern Methodist Univ., Dallas, TX (United States)
Publication Date:
OSTI Identifier:
Report Number(s):
Journal ID: ISSN 0018-9499
DOE Contract Number:
Resource Type:
Journal Article
Resource Relation:
Journal Name: IEEE Transactions on Nuclear Science; Journal Volume: 62; Journal Issue: 3
Institute of Electrical and Electronics Engineers (IEEE)
Research Org:
Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
Sponsoring Org:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
Country of Publication:
United States
43 PARTICLE ACCELERATORS; cryogenic electronics; degradation; hot-carrier degradation; MOSFET