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Title: Determining collective barrier operation skew in a parallel computer

Patent ·
OSTI ID:1226812

Determining collective barrier operation skew in a parallel computer that includes a number of compute nodes organized into an operational group includes: for each of the nodes until each node has been selected as a delayed node: selecting one of the nodes as a delayed node; entering, by each node other than the delayed node, a collective barrier operation; entering, after a delay by the delayed node, the collective barrier operation; receiving an exit signal from a root of the collective barrier operation; and measuring, for the delayed node, a barrier completion time. The barrier operation skew is calculated by: identifying, from the compute nodes' barrier completion times, a maximum barrier completion time and a minimum barrier completion time and calculating the barrier operation skew as the difference of the maximum and the minimum barrier completion time.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
9,195,516
Application Number:
13/308,917
OSTI ID:
1226812
Resource Relation:
Patent File Date: 2011 Dec 01
Country of Publication:
United States
Language:
English

References (7)

Uniform load distributing method for use in executing parallel processing in parallel computer patent July 1996
Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks patent July 2012
Synchronization of distributed simulation nodes by keeping timestep schedulers in lockstep patent-application May 2003
Effective use of a hardware barrier synchronization register for protocol synchronization patent-application March 2008
Determining When a Set of Compute Nodes Participating in a Barrier Operation on a Parallel Computer are Ready to Exit the Barrier Operation patent-application February 2009
System and Method for Providing a Fully Non-Blocking Switch in a Supernode of a Multi-Tiered Full-Graph Interconnect Architecture patent-application March 2009
Handling potential deadlocks and correctness problems of reduce operations in parallel systems patent-application March 2009

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97 MATHEMATICS AND COMPUTING