EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches
To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.
- Publication Date:
- OSTI Identifier:
- DOE Contract Number:
- Resource Type:
- Resource Relation:
- Conference: 2nd USENIX Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW), Broomsfield, CO, USA, 20141005, 20141005
- Research Org:
- Oak Ridge National Laboratory (ORNL)
- Sponsoring Org:
- SC USDOE - Office of Science (SC)
- Country of Publication:
- United States
- Non-volatile memory; ReRAM; wear-leveling; intra-set write variation; cache lifetime; write endurance
Enter terms in the toolbar above to search the full text of this document for pages containing specific keywords.