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Title: Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

Patent ·
OSTI ID:1156946
;

A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,832,415
Application Number:
12/984,329
OSTI ID:
1156946
Country of Publication:
United States
Language:
English

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Cited By (1)

Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests patent September 2014

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97 MATHEMATICS AND COMPUTING