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Title: Improving energy efficiency of Embedded DRAM Caches for High-end Computing Systems

With increasing system core-count, the size of last level cache (LLC) has increased and since SRAM consumes high leakage power, power consumption of LLCs is becoming a significant fraction of processor power consumption. To address this, researchers have used embedded DRAM (eDRAM) LLCs which consume low-leakage power. However, eDRAM caches consume a significant amount of energy in the form of refresh energy. In this paper, we propose ESTEEM, an energy saving technique for embedded DRAM caches. ESTEEM uses dynamic cache reconfiguration to turn-off a portion of the cache to save both leakage and refresh energy. It logically divides the cache sets into multiple modules and turns-off possibly different number of ways in each module. Microarchitectural simulations confirm that ESTEEM is effective in improving performance and energy efficiency and provides better results compared to a recently-proposed eDRAM cache energy saving technique, namely Refrint. For single and dual-core simulations, the average saving in memory subsystem (LLC+main memory) on using ESTEEM is 25.8% and 32.6%, respectively and average weighted speedup are 1.09X and 1.22X, respectively. Additional experiments confirm that ESTEEM works well for a wide-range of system parameters.
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  1. ORNL
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Conference: 23rd International ACM Symposium on High Performance Parallel and Distributing Computing (HPDC), Vancouver, Canada, 20140623, 20140627
Research Org:
Oak Ridge National Laboratory (ORNL)
Sponsoring Org:
SC USDOE - Office of Science (SC)
Country of Publication:
United States
Embedded DRAM (eDRAM) cache; low-power; cache reconfiguration; refresh energy saving; leakage energy saving