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Title: A Hybrid Approach for Parallel Transistor-Level Full-Chip Circuit Simulation.

Abstract not provided.
Authors:
;
Publication Date:
OSTI Identifier:
1140710
Report Number(s):
SAND2014-0224C
Journal ID: ISSN 0302--9743; 493349
DOE Contract Number:
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Journal Volume: 8969; Conference: Proposed for presentation at the International Meeting on High Performance Computing for Computational Science held June 30 - July 3, 2014 in Eugene, OR.
Research Org:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE National Nuclear Security Administration (NNSA)
Country of Publication:
United States
Language:
English