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Title: A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight their similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.
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  1. ORNL
Publication Date:
OSTI Identifier:
DOE Contract Number:
Resource Type:
Journal Article
Resource Relation:
Journal Name: IEEE Transactions on Parallel and Distributed Systems
Research Org:
Oak Ridge National Laboratory (ORNL)
Sponsoring Org:
SC USDOE - Office of Science (SC)
Country of Publication:
United States
Review; classification; embedded DRAM (eDRAM); non-volatile memory (NVM); spin-transfer torque RAM (STT-RAM); resistive RAM (RRAM); phase change RAM (PCM); domain wall memory (DWM); emerging memory technologies