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Title: WriteSmoothing: Improving Lifetime of Non-volatile Caches Using Intra-set Wear-leveling

Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased. Since SRAM consumes high leakage power, researchers have explored use of non-volatile memories (NVMs) for designing caches as they provide high density and consume low leakage power. However, since NVMs have low write-endurance and the existing cache management policies are write variation-unaware, effective wear-leveling techniques are required for achieving reasonable cache lifetimes using NVMs. We present WriteSmoothing, a technique for mitigating intra-set write variation in NVM caches. WriteSmoothing logically divides the cache-sets into multiple modules. For each module, WriteSmoothing collectively records number of writes in each way for any of the sets. It then periodically makes most frequently written ways in a module unavailable to shift the write-pressure to other ways in the sets of the module. Extensive simulation results have shown that on average, for single and dual-core system configurations, WriteSmoothing improves cache lifetime by 2.17X and 2.75X, respectively. Also, its implementation overhead is small and it works well for a wide range of algorithm and system parameters.
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  1. ORNL
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Conference: ACM Great Lakes Symposium on VLSI, Houston, TX, USA, 20140521, 20140523
Research Org:
Oak Ridge National Laboratory (ORNL)
Sponsoring Org:
SC USDOE - Office of Science (SC)
Country of Publication:
United States
Non-volatile memory; cache; wear-leveling; lifetime