skip to main content

SciTech ConnectSciTech Connect

Title: Heap/stack guard pages using a wakeup unit

A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
Authors:
; ;
Publication Date:
OSTI Identifier:
1129892
Report Number(s):
8,713,294
12/696,817
DOE Contract Number:
B554331
Resource Type:
Patent
Research Org:
International Business Machines Corporation, Armonk, NY, USA
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING