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Title: Multiprocessor switch with selective pairing

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus
Authors:
; ;
Publication Date:
OSTI Identifier:
1126499
Report Number(s):
8,671,311
13/027,882
DOE Contract Number:
B554331
Resource Type:
Patent
Research Org:
International Business Machines Corporation, Armonk, NY, USA
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING