Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
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patent
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February 1995 |
Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
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patent
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April 1998 |
Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corresponding locations of another memory
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patent
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May 1998 |
Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
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patent
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October 1999 |
Method of non-intrusive testing for a process control interface system having triply redundant remote field units
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patent
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October 1999 |
Fault tolerant computer system
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patent
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October 2000 |
Error self-checking and recovery using lock-step processor pair architecture
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patent
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May 2002 |
Multiprocessor with pair-wise high reliability mode, and method therefore
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patent
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August 2004 |
Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step
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patent
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March 2005 |
System recovery from errors for processor and associated components
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patent
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September 2005 |
Emulation interface system
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patent
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June 2006 |
Apparatus and methods for fault-tolerant computing using a switching fabric
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patent
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June 2006 |
Method and apparatus for communicating information between lock stepped processors
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patent
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December 2006 |
Architectural support for selective use of high-reliability mode in a computer system
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patent
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October 2007 |
Core-level processor lockstepping
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patent
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October 2007 |
Core redundancy in a chip multiprocessor for highly reliable systems
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patent
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February 2008 |
Synchronous electronic control system and system control method
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patent
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March 2008 |
Method and apparatus for seeding differences in lock-stepped processors
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patent
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July 2008 |
Method and system of executing duplicate copies of a program in lock step
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patent
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September 2008 |
Cross correlation tool for automated portfolio descriptive statistics
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patent
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April 2009 |
System and method for a distributed crossbar network using a plurality of crossbars
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patent
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July 2009 |
Cache coherency during resynchronization of self-correcting computer
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patent
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November 2009 |
Method and device for switching over in a computer system having at least two execution units
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patent
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February 2010 |
Selective availability in processor systems
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patent
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May 2011 |
Auxiliary circuit structure in a split-lock dual processor system
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patent
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November 2011 |
System recovery from errors for processor and associated components
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patent-application
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October 2002 |
High reliability system, redundant construction control method, and program
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patent-application
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September 2005 |
Delegated write for race avoidance in a processor
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patent-application
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October 2005 |
Diagnostic memory dump method in a redundant processor
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patent-application
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October 2005 |
System and method of executing program threads in a multi-threaded processor
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patent-application
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October 2006 |
Method and apparatus for communicating information between lock stepped processors
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patent-application
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March 2007 |
System with Configurable Functional Units and Method
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patent-application
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February 2010 |
Resource Sharing to Reduce Implementation Costs in a Multicore Processor
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patent-application
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July 2011 |
A Genetic Algorithm for Reliability-Oriented Task Assignment With<tex>$widetildek$</tex>Duplications in Distributed Systems
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journal
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March 2006 |
The Stanford Hydra CMP
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journal
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January 2000 |
Transactional Memory Coherence and Consistency
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journal
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March 2004 |