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Title: Addressing Inter-set Write-Variation for Improving Lifetime of Non-Volatile Caches

We propose a technique which minimizes inter-set write variation in NVM caches for improving its lifetime. Our technique uses cache coloring scheme to add a software-controlled mapping layer between groups of physical pages (called memory regions) and cache sets. Periodically, the number of writes to different colors of the cache is computed and based on this result, the mapping of a few colors is changed to channel the write traffic to least utilized cache colors. This change helps to achieve wear-leveling.
 [1] ;  [1]
  1. ORNL
Publication Date:
OSTI Identifier:
DOE Contract Number:
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Resource Relation:
Conference: 5th Annual Non-Volatile Memories Workshop 2014, San Diego, CA, USA, 20140309, 20140309
Research Org:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org:
USDOE Office of Science (SC)
Country of Publication:
United States
non-volatile memory; cache; wear-leveling; computer architecture