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Title: Efficiency of static core turn-off in a system-on-a-chip with variation

A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.
Authors:
; ; ; ; ; ; ;
Publication Date:
OSTI Identifier:
1107625
Report Number(s):
8,571,847
12/727,984
DOE Contract Number:
B554331
Resource Type:
Patent
Research Org:
International Business Machines Corporation (Armonk, NY)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING