skip to main content

Title: Low delay and area efficient soft error correction in arbitration logic

There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.
Authors:
Publication Date:
OSTI Identifier:
1093240
Report Number(s):
8,533,567
12/852,801
DOE Contract Number:
B554331
Resource Type:
Patent
Research Org:
OSTI (Office of Scientific and Technical Information, Oak Ridge, TN)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING