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Title: Low delay and area efficient soft error correction in arbitration logic

Patent ·
OSTI ID:1093240

There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,533,567
Application Number:
12/852,801
OSTI ID:
1093240
Resource Relation:
Patent File Date: 2010 Aug 09
Country of Publication:
United States
Language:
English

References (18)

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conference October 2008
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Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same patent April 2005
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Self-resetting, self-correcting latches patent June 2010
A TMR Scheme for SEU Mitigation in Scan Flip-Flops conference March 2007
Error Detecting and Error Correcting Codes journal April 1950
Logic soft error rate prediction and improvement patent January 2010

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Related Subjects

97 MATHEMATICS AND COMPUTING