Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Chen, C.; Gong, D.; Guo, D.; Huang, G.; Huang, X.; Kulis, S.; Leroux, P; Liu, C.; Liu, T.; Moreira, P.; Prinzie, J.; Sun, Q.; Wang, P.; Xiao, L.; Ye, J.

doi:10.1088/1748-0221/15/03/t03005

Title: Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Abstract

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

Authors:

Chen, C. ^[1]; Gong, D. ^[2]; Guo, D. ^[3]; Huang, G. ^[3]; Huang, X. ^[1]; Kulis, S. ^[4]; Leroux, P ^[5]; Liu, C. ^[2]; Liu, T. ^[2]; Moreira, P. ^[4]; Prinzie, J. ^[5]; Sun, Q. ^[2]; Wang, P. ^[2]; Xiao, L. ^[3]; Ye, J. ^[2]

Central China Normal Univ., Hubei (China); Southern Methodist Univ., Dallas, TX (United States)
Southern Methodist Univ., Dallas, TX (United States)
Central China Normal Univ., Hubei (China)
European Organization for Nuclear Research (CERN), Geneva (Switzerland)
KU Leuven (Switzerland)

Publication Date:: Mon Mar 30 00:00:00 EDT 2020

Research Org.:: Harvard Univ., Cambridge, MA (United States)

Sponsoring Org.:: USDOE Office of Science (SC), High Energy Physics (HEP)

OSTI Identifier:: 1685045

Grant/Contract Number:: SC0007881; AC02-05CH11231

Resource Type:: Accepted Manuscript

Journal Name:: Journal of Instrumentation

Additional Journal Information:: Journal Volume: 15; Journal Issue: 03; Journal ID: ISSN 1748-0221

Publisher:: Institute of Physics (IOP)

Country of Publication:: United States

Language:: English

Subject:: 47 OTHER INSTRUMENTATION; Analogue electronic circuits; Electronic detector readout concepts (solid-state); Front-end electronics for detector readout; VLSI circuits

Citation Formats


                    Chen, C., Gong, D., Guo, D., Huang, G., Huang, X., Kulis, S., Leroux, P, Liu, C., Liu, T., Moreira, P., Prinzie, J., Sun, Q., Wang, P., Xiao, L., and Ye, J. Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade.  United States: N. p., 2020. 
Web.  doi:10.1088/1748-0221/15/03/t03005.

Copy to clipboard


                    Chen, C., Gong, D., Guo, D., Huang, G., Huang, X., Kulis, S., Leroux, P, Liu, C., Liu, T., Moreira, P., Prinzie, J., Sun, Q., Wang, P., Xiao, L., & Ye, J. Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade.  United States.  https://doi.org/10.1088/1748-0221/15/03/t03005

Copy to clipboard


                    Chen, C., Gong, D., Guo, D., Huang, G., Huang, X., Kulis, S., Leroux, P, Liu, C., Liu, T., Moreira, P., Prinzie, J., Sun, Q., Wang, P., Xiao, L., and Ye, J. Mon .  
"Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade".  United States.  https://doi.org/10.1088/1748-0221/15/03/t03005.  https://www.osti.gov/servlets/purl/1685045.

Copy to clipboard


                    
@article{osti_1685045,

  title        = {Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade},

  author       = {Chen, C. and Gong, D. and Guo, D. and Huang, G. and Huang, X. and Kulis, S. and Leroux, P and Liu, C. and Liu, T. and Moreira, P. and Prinzie, J. and Sun, Q. and Wang, P. and Xiao, L. and Ye, J.},

  abstractNote = {We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.},

  doi          = {10.1088/1748-0221/15/03/t03005},

  journal      = {Journal of Instrumentation},

  number       = 03,

  volume       = 15,

  place        = {United States},

  year         = {Mon Mar 30 00:00:00 EDT 2020},

  month        = {Mon Mar 30 00:00:00 EDT 2020}

}

Copy to clipboard

Journal Article:

Free Publicly Available Full Text

Accepted Manuscript (DOE)

Publisher's Version of Record

https://doi.org/10.1088/1748-0221/15/03/t03005

Other availability

Search WorldCat to find libraries that may hold this journal

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers
journal, December 2000

Sackinger, E.; Fischer, W. C.
IEEE Journal of Solid-State Circuits, Vol. 35, Issue 12
DOI: 10.1109/4.890301

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS
journal, March 2015

You, Y.; Chen, J.; Feng, Y.
Journal of Instrumentation, Vol. 10, Issue 03
DOI: 10.1088/1748-0221/10/03/C03013

A 4.9-GHz low power, low jitter, LC phase locked loop
journal, December 2010

Liu, T.
Journal of Instrumentation, Vol. 5, Issue 12
DOI: 10.1088/1748-0221/5/12/C12045

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
journal, May 2001

Savoj, J.; Razavi, B.
IEEE Journal of Solid-State Circuits, Vol. 36, Issue 5
DOI: 10.1109/4.918913

A low noise clock generator for high-resolution time-to-digital convertors
journal, February 2016

Prinzie, J.; Christiaensen, J.; Moreira, P.
Journal of Instrumentation, Vol. 11, Issue 02
DOI: 10.1088/1748-0221/11/02/C02038

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers
journal, September 2007

Gondi, S. .; Razavi, B. .
IEEE Journal of Solid-State Circuits, Vol. 42, Issue 9
DOI: 10.1109/JSSC.2007.903076

A New Adaptive Technique for Transmitter Pre-Emphasis and Receiver Equalization in a High-Speed Backplane Environment
conference, January 2006

Baskaran, L. P.; Agili, S.; Morales, A.
2006 Digest of Technical Papers International Conference on Consumer Electronics
DOI: 10.1109/ICCE.2006.1598466

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology
journal, January 2018

Prinzie, Jeffrey; Christiansen, Jorgen; Moreira, Paulo
IEEE Transactions on Nuclear Science, Vol. 65, Issue 1
DOI: 10.1109/TNS.2017.2764501

Similar Records in DOE PAGES and OSTI.GOV collections:

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

Journal Article Zhang, L. ; Gong, D. ; Liu, T. ; ... - TBD

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signalsmore »« less
Full Text Available
A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments

Journal Article Huang, Xing ; Gong, Datao ; Hou, Suen ; ... - IEEE Transactions on Nuclear Science

We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gbps (DLAS10) and three Miniature Optical Transmitter/Receiver/Transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two Transmitter Optical Sub-Assemblies (TOSAs) of Vertical Cavity Surface Emitting Lasers (VCSELs), receive the signals from two Receiver Optical Sub-Assemblies (ROSAs) that have no embedded limiting amplifiers, or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input Continuous Time Linear Equalizer (CTLE), a four-stage limiting amplifier (LA), and an output driver. The LA amplifiesmore »« less
https://doi.org/10.1109/tns.2021.3086481

Full Text Available
A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments

Journal Article Zhang, L. ; et al. - JINST

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 2more »« less
https://doi.org/10.1088/1748-0221/17/03/C03011

Full Text Available
Radiation-hard miniature optical engine with high bandwidth

Journal Article Tar, B. ; Gan, K. K. ; Buchholz, P. ; ... - Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment

Future silicon trackers will be operated in an intense radiation environment and require large volumes of data to be transmitted off detector. In addition, the optical modules must be of low mass in order to limit multiple scattering and nuclear interactions that would degrade the overall performance of the detector. Here, we present a miniature optical engine that satisfies these constraints. The optical engine consists of an ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. Two ASICs are designed to operate a 12-channel VCSEL array at 1.28 or 5.12 Gb/s per channel, which yieldsmore »« less
https://doi.org/10.1016/j.nima.2020.164377

Full Text Available
A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments

Conference Zhang, Li ; Gong, Datao ; Hou, Suen ; ...

We present the design principle and test results of a data transmitting ASIC, GBS20, for particle physics experiments. The goal of GBS20 will be an ASIC that employs two serializers each from the 10.24 Gbps lpGBT SerDes, sharing the PLL also from lpGBT. A PAM4 encoder plus a VCSEL driver will be implemented in the same die to use the same clock system, eliminating the need of CDRs in the PAM4 encoder. This way the transmitter module, GBT20, developed using the GBS20 ASIC, will have the exact lpGBT data interface and transmission protocol, with an output up to 20.48 Gbpsmore »« less
Full Text Available

Similar Records

Title: Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Abstract

Citation Formats

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers journal, December 2000

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS journal, March 2015

A 4.9-GHz low power, low jitter, LC phase locked loop journal, December 2010

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector journal, May 2001

A low noise clock generator for high-resolution time-to-digital convertors journal, February 2016

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers journal, September 2007

A New Adaptive Technique for Transmitter Pre-Emphasis and Receiver Equalization in a High-Speed Backplane Environment conference, January 2006

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology journal, January 2018

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers
journal, December 2000

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS
journal, March 2015

A 4.9-GHz low power, low jitter, LC phase locked loop
journal, December 2010

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
journal, May 2001

A low noise clock generator for high-resolution time-to-digital convertors
journal, February 2016

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers
journal, September 2007

A New Adaptive Technique for Transmitter Pre-Emphasis and Receiver Equalization in a High-Speed Backplane Environment
conference, January 2006

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology
journal, January 2018