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Title: Optimization on fixed low latency implementation of the GBT core in FPGA

Abstract

We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lowermore » fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.« less

Authors:
 [1];  [1];  [1];  [1];  [1]
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  1. Brookhaven National Lab. (BNL), Upton, NY (United States)
Publication Date:
Research Org.:
Brookhaven National Lab. (BNL), Upton, NY (United States)
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP)
OSTI Identifier:
1424952
Report Number(s):
BNL-200039-2018-JAAM
Journal ID: ISSN 1748-0221; TRN: US1801975
Grant/Contract Number:  
SC0012704
Resource Type:
Accepted Manuscript
Journal Name:
Journal of Instrumentation
Additional Journal Information:
Journal Volume: 12; Journal Issue: 07; Journal ID: ISSN 1748-0221
Publisher:
Institute of Physics (IOP)
Country of Publication:
United States
Language:
English
Subject:
47 OTHER INSTRUMENTATION; Fixed low latency transmission; GBT link; Transceiver in FPGA

Citation Formats

Chen, K., Chen, H., Wu, W., Xu, H., and Yao, L. Optimization on fixed low latency implementation of the GBT core in FPGA. United States: N. p., 2017. Web. doi:10.1088/1748-0221/12/07/P07011.
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Chen, K., Chen, H., Wu, W., Xu, H., & Yao, L. Optimization on fixed low latency implementation of the GBT core in FPGA. United States. https://doi.org/10.1088/1748-0221/12/07/P07011
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Chen, K., Chen, H., Wu, W., Xu, H., and Yao, L. Tue . "Optimization on fixed low latency implementation of the GBT core in FPGA". United States. https://doi.org/10.1088/1748-0221/12/07/P07011. https://www.osti.gov/servlets/purl/1424952.
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@article{osti_1424952,
title = {Optimization on fixed low latency implementation of the GBT core in FPGA},
author = {Chen, K. and Chen, H. and Wu, W. and Xu, H. and Yao, L.},
abstractNote = {We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.},
doi = {10.1088/1748-0221/12/07/P07011},
journal = {Journal of Instrumentation},
number = 07,
volume = 12,
place = {United States},
year = {Tue Jul 11 00:00:00 EDT 2017},
month = {Tue Jul 11 00:00:00 EDT 2017}
}
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Publisher's Version of Record
https://doi.org/10.1088/1748-0221/12/07/P07011
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Works referenced in this record:

The GBT-FPGA core: features and challenges
journal, March 2015

FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades
journal, December 2015

Optimizing latency in Xilinx FPGA implementations of the GBT
journal, December 2010

TTC distribution for LHC detectors
journal, June 1998

  • Taylor, B. G.
  • IEEE Transactions on Nuclear Science, Vol. 45, Issue 3
  • DOI: 10.1109/23.682644

Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs
journal, February 2011

  • Giordano, Raffaele; Aloisio, Alberto
  • IEEE Transactions on Nuclear Science, Vol. 58, Issue 1
  • DOI: 10.1109/TNS.2010.2101083

High-speed, fixed-latency serial links with Xilinx FPGAs
journal, February 2014

  • Liu, Xue; Deng, Qing-xu; Hou, Bo-ning
  • Journal of Zhejiang University SCIENCE C, Vol. 15, Issue 2
  • DOI: 10.1631/jzus.C1300249

The development of the global feature extractor for the LHC Run-3 upgrade of the L1 calorimeter trigger system
conference, June 2016

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