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Title: A 2.1 GS/s 2-Channel Pipeline-SAR ADC With Speed-Enhanced Bootstrap Switch and Low-Latency SAR Logic

Journal Article · · IEEE Access
ORCiD logo [1]; ORCiD logo [1]; ORCiD logo [2]; ORCiD logo [1]
  1. Department of Electrical and Computer Engineering, Southern Methodist University, Dallas, TX, USA
  2. Broadcom Inc., Palo Alto, CA, USA
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Not Available

Sponsoring Organization:
USDOE
Grant/Contract Number:
SC0022353
OSTI ID:
2531120
Journal Information:
IEEE Access, Journal Name: IEEE Access Vol. 13; ISSN 2169-3536
Publisher:
Institute of Electrical and Electronics EngineersCopyright Statement
Country of Publication:
United States
Language:
English

References (36)

Analog-to-digital converters and time-to-digital converters for high-energy physics experiments journal December 2023
A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS journal January 2024
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing conference April 2022
A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration conference September 2019
A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors conference September 2023
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS conference February 2014
17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input conference February 2023
10.3 A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer conference February 2023
10.2 A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness conference February 2023
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS journal December 2006
A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing journal August 2010
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC journal November 2012
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS journal December 2013
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC journal February 2015
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC journal February 2016
A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer journal June 2017
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation journal June 2018
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier journal February 2020
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS journal January 2020
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration journal November 2020
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration journal September 2021
A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples journal June 2022
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier journal December 2022
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch journal September 2019
Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI journal September 2005
A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step journal August 2022
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing journal September 2018
A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS journal September 2019
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM S in 65-nm CMOS journal February 2022
A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS conference June 2010
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither conference June 2016
27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth conference January 2016
27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS conference January 2016
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology journal December 2017
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET conference June 2018
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS conference June 2023

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