Implementing a Hardware Testbed Using 3-Level ANPC Software Defined Inverters for Fault Analysis of a Transmission Network
- Univ. of Central Florida, Orlando, FL (United States); University of Central Florida
- Electric Power Research Inst. (EPRI), Knoxville, TN (United States)
- Siemens Technology, Princeton, NJ (United States)
- Siemens Technology, Erlangen (Germany)
- Univ. of Central Florida, Orlando, FL (United States)
In this paper, we propose the implementation of a hardware testbed using 3-level active neutral point clamped (ANPC) software-defined inverters for fault analysis. A test case transmission network equipped with two grid forming (GFM) inverters and four resistive loads is considered in this research. Firstly, grid forming control laws including PI feedback control and droop control are implemented to operate the inverters in parallel. Then, we implement a fault ride-through (FRT) logic and perform a simulation of the test system by applying a three-phase fault. Simulation results show the effectiveness of the fault recovery algorithm upon clearance of the fault. Finally, a 3-level ANPC software-defined inverter is programmed with required control laws and characterized through various lab experiments.
- Research Organization:
- Univ. of Central Florida, Orlando, FL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC); USDOE Advanced Research Projects Agency - Energy (ARPA-E)
- Grant/Contract Number:
- EE0009028; AR0001570
- OSTI ID:
- 2324973
- Journal Information:
- Proceedings of IEEE Southeastcon, Journal Name: Proceedings of IEEE Southeastcon Vol. 2024; ISSN 1091-0050; ISSN 1558-058X
- Publisher:
- IEEECopyright Statement
- Country of Publication:
- United States
- Language:
- English
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