FPGA-based HPC accelerators: An evaluation on performance and energy efficiency
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- DEIB, Politecnico di Milano (Italy)
Hardware specialization is a promising direction for the future of digital computing. Reconfigurable technologies enable hardware specialization with modest non-recurring engineering cost, but their performance and energy efficiency compared to state-of-the-art processor architectures remain an open question. In this article, we use FPGAs to evaluate the benefits of building specialized hardware for numerical kernels found in scientific applications. In order to properly evaluate performance, we not only compare Intel Arria 10 and Xilinx U280 performance against Intel Xeon, Intel Xeon Phi, and NVIDIA V100 GPUs, but we also extend the Empirical Roofline Toolkit (ERT) to FPGAs in order to assess our results in terms of the Roofline model. We show design optimization and tuning techniques for peak FPGA performance at reasonable hardware usage and power consumption. As FPGA peak performance is known to be far less than that of a GPU, we also benchmark the energy efficiency of each platform for the scientific kernels comparing against microbenchmark and technological limits. Results show that while FPGAs struggle to compete in absolute terms with GPUs on memory- and compute-intensive kernels, they require far less power and can deliver nearly the same energy efficiency.
- Research Organization:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR)
- Grant/Contract Number:
- AC02-05CH11231
- OSTI ID:
- 1959989
- Journal Information:
- Concurrency and Computation. Practice and Experience, Journal Name: Concurrency and Computation. Practice and Experience Journal Issue: 20 Vol. 34; ISSN 1532-0626
- Publisher:
- WileyCopyright Statement
- Country of Publication:
- United States
- Language:
- English
Striped Smith-Waterman speeds database searches six times over other SIMD implementations
|
journal | November 2006 |
On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms
|
conference | June 2014 |
Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA?
|
conference | April 2012 |
Understanding Performance Differences of FPGAs and GPUs
|
conference | April 2018 |
Shuhai: Benchmarking High Bandwidth Memory On FPGAS
|
conference | May 2020 |
Performance comparison of FPGA, GPU and CPU in image processing
|
conference | August 2009 |
Trends of CPU, GPU and FPGA for high-performance computing
|
conference | September 2014 |
FPGA vs. GPU for sparse matrix vector multiply
|
conference | December 2009 |
Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite
|
conference | November 2020 |
Rodinia: A benchmark suite for heterogeneous computing
|
conference | October 2009 |
A Roofline Model of Energy
|
conference | May 2013 |
merAligner: A Fully Parallel Sequence Aligner
|
conference | May 2015 |
BLAS Comparison on FPGA, CPU and GPU
|
conference | July 2010 |
An Empirical Roofline Methodology for Quantitatively Assessing Performance Portability
|
conference | November 2018 |
The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing
|
conference | November 2020 |
Accelerating Compute-Intensive Applications with GPUs and FPGAs
|
conference | June 2008 |
Evaluating and Optimizing OpenCL Kernels for High Performance Computing with FPGAs
|
conference | November 2016 |
Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores
|
journal | January 2017 |
Impact of modern memory subsystems on cache optimizations for stencil computations
|
conference | January 2005 |
Roofline: an insightful visual performance model for multicore architectures
|
journal | April 2009 |
Let there be light!
|
conference | June 2011 |
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?
|
conference | February 2017 |
The Power-optimised Software Envelope
|
journal | June 2019 |
Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis
|
conference | February 2020 |
A CAD-based methodology to optimize HLS code via the roofline model
|
conference | November 2020 |
Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools
|
journal | January 2013 |
Similar Records
Evaluating and Optimizing OpenCL Base64 Data Unpacking Kernel with FPGA
Population Count on Intel® CPU, GPU, and FPGA