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Title: Analog architectures for neural network acceleration based on non-volatile memory

Authors:
ORCiD logo [1]; ORCiD logo [1]; ORCiD logo [1]; ORCiD logo [1]; ORCiD logo [1]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA); USDOE Laboratory Directed Research and Development (LDRD) Program
OSTI Identifier:
1668360
Alternate Identifier(s):
OSTI ID: 1637994
Report Number(s):
SAND-2020-5154J
Journal ID: ISSN 1931-9401; 686136
Grant/Contract Number:  
AC04-94AL85000; NA0003525
Resource Type:
Accepted Manuscript
Journal Name:
Applied Physics Reviews
Additional Journal Information:
Journal Volume: 7; Journal Issue: 3; Journal ID: ISSN 1931-9401
Publisher:
American Institute of Physics (AIP)
Country of Publication:
United States
Language:
English

Citation Formats

Xiao, T. Patrick, Bennett, Christopher H., Feinberg, Ben, Agarwal, Sapan, and Marinella, Matthew J. Analog architectures for neural network acceleration based on non-volatile memory. United States: N. p., 2020. Web. doi:10.1063/1.5143815.
Xiao, T. Patrick, Bennett, Christopher H., Feinberg, Ben, Agarwal, Sapan, & Marinella, Matthew J. Analog architectures for neural network acceleration based on non-volatile memory. United States. doi:10.1063/1.5143815.
Xiao, T. Patrick, Bennett, Christopher H., Feinberg, Ben, Agarwal, Sapan, and Marinella, Matthew J. Thu . "Analog architectures for neural network acceleration based on non-volatile memory". United States. doi:10.1063/1.5143815.
@article{osti_1668360,
title = {Analog architectures for neural network acceleration based on non-volatile memory},
author = {Xiao, T. Patrick and Bennett, Christopher H. and Feinberg, Ben and Agarwal, Sapan and Marinella, Matthew J.},
abstractNote = {},
doi = {10.1063/1.5143815},
journal = {Applied Physics Reviews},
number = 3,
volume = 7,
place = {United States},
year = {2020},
month = {7}
}

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New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing
journal, June 2014

  • Truong, Son Ngoc; Min, Kyeong-Sik
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Memristor-Based Circuit Design for Multilayer Neural Networks
journal, February 2018

  • Zhang, Yang; Wang, Xiaoping; Friedman, Eby G.
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Fully hardware-implemented memristor convolutional neural network
journal, January 2020


An Open-Source Tool Set Enabling Analog-Digital-Software Co-Design
journal, February 2016

  • Collins, Michelle; Hasler, Jennifer; George, Suma
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Experimental Demonstration of Feature Extraction and Dimensionality Reduction Using Memristor Networks
journal, April 2017


Optimal unsupervised learning in a single-layer linear feedforward neural network
journal, January 1989


Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory
journal, July 2017

  • Narayanan, P.; Fumarola, A.; Sanches, L. L.
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Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
journal, October 2015


Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration
journal, June 2015

  • Kadetotad, Deepak; Xu, Zihan; Mohanty, Abinash
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Streaming Batch Eigenupdates for Hardware Neural Networks
journal, August 2019

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Mixed-Precision Deep Learning Based on Computational Memory
journal, May 2020

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  • Frontiers in Neuroscience, Vol. 14
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Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)
conference, December 2015

  • Burr, G. W.; Narayanan, P.; Shelby, R. M.
  • 2015 IEEE International Electron Devices Meeting (IEDM)
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Visual Pattern Extraction Using Energy-Efficient “2-PCM Synapse” Neuromorphic Architecture
journal, August 2012

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Physical Realization of a Supervised Learning System Built with Organic Memristive Synapses
journal, September 2016

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Algorithm for Training Neural Networks on Resistive Device Arrays
journal, February 2020


Analog high resistance bilayer RRAM device for hardware acceleration of neuromorphic computation
journal, November 2018

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Parasitic Effect Analysis in Memristor-Array-Based Neuromorphic Systems
journal, January 2018

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Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator
conference, January 2019

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  • ASPDAC '19: 24th Asia and South Pacific Design Automation Conference, Proceedings of the 24th Asia and South Pacific Design Automation Conference
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Computation-oriented fault-tolerance schemes for RRAM computing systems
conference, January 2017

  • Huangfu, Wenqin; Xia, Lixue; Cheng, Ming
  • 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
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Neuromorphic computing with multi-memristive synapses
journal, June 2018


Contrasting Advantages of Learning With Random Weights and Backpropagation in Non-Volatile Memory Neural Networks
journal, January 2019


Random synaptic feedback weights support error backpropagation for deep learning
journal, November 2016

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An approximate backpropagation learning rule for memristor based neural networks using synaptic plasticity
journal, May 2017


NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
journal, December 2018

  • Chen, Pai-Yu; Peng, Xiaochen; Yu, Shimeng
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