Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs

Shah, Shahil D.; Koralewicz, Przemyslaw J.; Gevorgian, Vahan; Parsa, Leila

doi:10.1109/TEC.2019.2954112

Title: Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs

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Abstract

This report introduces signal-flow graphs for linear time-periodic systems to streamline and visually describe the frequency-domain modeling of complex phase-locked loop (PLL) systems used in grid-connected converters. Small-signal modeling using the proposed graphs is demonstrated for two commonly used single-phase PLL structures: SOGI-PLL and Park-PLL. Loop-gain models are developed for these PLLs to evaluate how an orthogonal signal generator (OSG), which is required in single-phase PLLs using the synchronous reference frame (SRF) architecture, modifies the PLL loop-gain compared to that of a three-phase SRF-PLL, which does not require an OSG. It is shown that the OSG in the SOGI-PLL and Park-PLL introduces significant phase-lag in the PLL loop-gain, limiting the maximum bandwidth for which either PLL can be designed. Slow frequency adaptation (SFA) of OSG is proposed as a solution to mitigate the influence of the OSG dynamics on the PLL loop-gain. Experimental results are presented to validate the developed loop-gain models and show that the proposed SFA-SOGI-PLL and SFA-Park-PLL have improved transient performance, they do not suffer from the bandwidth limit, and they also preserve the steady-state performance of the standard SOGI-PLL and Park-PLL.

Authors:

^[1];

^[1]; Gevorgian, Vahan ^[1]; Parsa, Leila ^[2]

National Renewable Energy Lab. (NREL), Golden, CO (United States)
Rensselaer Polytechnic Inst., Troy, NY (United States)

Publication Date:: Mon Nov 18 00:00:00 EST 2019

Research Org.:: National Renewable Energy Lab. (NREL), Golden, CO (United States)

Sponsoring Org.:: USDOE Office of Energy Efficiency and Renewable Energy (EERE), Renewable Power Office. Solar Energy Technologies Office

OSTI Identifier:: 1603265

Report Number(s):: NREL/JA-5D00-74030
Journal ID: ISSN 0885-8969; MainId:20229;UUID:a6b58553-8581-e911-9c21-ac162d87dfe5;MainAdminID:8705

Grant/Contract Number:: AC36-08GO28308

Resource Type:: Accepted Manuscript

Journal Name:: IEEE Transactions on Energy Conversion

Additional Journal Information:: Journal Volume: 35; Journal Issue: 2; Journal ID: ISSN 0885-8969

Publisher:: IEEE

Country of Publication:: United States

Language:: English

Subject:: 24 POWER TRANSMISSION AND DISTRIBUTION; linear time-periodic (LTP) systems; small-signal stability; phase-locked loops; impedance modeling

Citation Formats


                    Shah, Shahil D., Koralewicz, Przemyslaw J., Gevorgian, Vahan, and Parsa, Leila. Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs.  United States: N. p., 2019. 
Web.  doi:10.1109/TEC.2019.2954112.

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                    Shah, Shahil D., Koralewicz, Przemyslaw J., Gevorgian, Vahan, & Parsa, Leila. Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs.  United States.  https://doi.org/10.1109/TEC.2019.2954112

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                    Shah, Shahil D., Koralewicz, Przemyslaw J., Gevorgian, Vahan, and Parsa, Leila. Mon .  
"Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs".  United States.  https://doi.org/10.1109/TEC.2019.2954112.  https://www.osti.gov/servlets/purl/1603265.

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@article{osti_1603265,

  title        = {Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs},

  author       = {Shah, Shahil D. and Koralewicz, Przemyslaw J. and Gevorgian, Vahan and Parsa, Leila},

  abstractNote = {This report introduces signal-flow graphs for linear time-periodic systems to streamline and visually describe the frequency-domain modeling of complex phase-locked loop (PLL) systems used in grid-connected converters. Small-signal modeling using the proposed graphs is demonstrated for two commonly used single-phase PLL structures: SOGI-PLL and Park-PLL. Loop-gain models are developed for these PLLs to evaluate how an orthogonal signal generator (OSG), which is required in single-phase PLLs using the synchronous reference frame (SRF) architecture, modifies the PLL loop-gain compared to that of a three-phase SRF-PLL, which does not require an OSG. It is shown that the OSG in the SOGI-PLL and Park-PLL introduces significant phase-lag in the PLL loop-gain, limiting the maximum bandwidth for which either PLL can be designed. Slow frequency adaptation (SFA) of OSG is proposed as a solution to mitigate the influence of the OSG dynamics on the PLL loop-gain. Experimental results are presented to validate the developed loop-gain models and show that the proposed SFA-SOGI-PLL and SFA-Park-PLL have improved transient performance, they do not suffer from the bandwidth limit, and they also preserve the steady-state performance of the standard SOGI-PLL and Park-PLL.},

  doi          = {10.1109/TEC.2019.2954112},

  journal      = {IEEE Transactions on Energy Conversion},

  number       = 2,

  volume       = 35,

  place        = {United States},

  year         = {Mon Nov 18 00:00:00 EST 2019},

  month        = {Mon Nov 18 00:00:00 EST 2019}

}

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