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Title: Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Abstract

The domain wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this work, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that, while the energy cost of systems driven by spin-transfer torque (STT) domain wall motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS sub-processor component. This result clarifies the path towards practical implementations of an all-magnetic processor system.

Authors:
 [1];  [1];  [2];  [1];  [1];  [1];  [3];  [2];  [4];  [1]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
  2. Univ. of Texas, Richardson, TX (United States)
  3. Arizona State Univ., Tempe, AZ (United States)
  4. Univ. of Texas, Austin, TX (United States)
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Sandia National Laboratories, Livermore, CA
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1595031
Report Number(s):
SAND-2019-14855J
Journal ID: ISSN 2329-9231; 682344
Grant/Contract Number:  
AC04-94AL85000; NA0003525
Resource Type:
Accepted Manuscript
Journal Name:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Additional Journal Information:
Journal Name: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits; Journal ID: ISSN 2329-9231
Country of Publication:
United States
Language:
English
Subject:
sprintronics; domain wall; magnetic logic; post-CMOS logic; benchmarking; magnetic tunnel junction

Citation Formats

Xiao, T. Patrick, Bennett, Christopher H., Hu, Xuan, Feinberg, Ben, Jacobs-Gedrim, Robin, Agarwal, Sapan, Brunhaver, John, Friedman, Joseph S., Incorvia, Jean Anne C., and Marinella, Matthew J. Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder. United States: N. p., 2019. Web. doi:10.1109/JXCDC.2019.2955016.
Xiao, T. Patrick, Bennett, Christopher H., Hu, Xuan, Feinberg, Ben, Jacobs-Gedrim, Robin, Agarwal, Sapan, Brunhaver, John, Friedman, Joseph S., Incorvia, Jean Anne C., & Marinella, Matthew J. Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder. United States. doi:10.1109/JXCDC.2019.2955016.
Xiao, T. Patrick, Bennett, Christopher H., Hu, Xuan, Feinberg, Ben, Jacobs-Gedrim, Robin, Agarwal, Sapan, Brunhaver, John, Friedman, Joseph S., Incorvia, Jean Anne C., and Marinella, Matthew J. Fri . "Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder". United States. doi:10.1109/JXCDC.2019.2955016. https://www.osti.gov/servlets/purl/1595031.
@article{osti_1595031,
title = {Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder},
author = {Xiao, T. Patrick and Bennett, Christopher H. and Hu, Xuan and Feinberg, Ben and Jacobs-Gedrim, Robin and Agarwal, Sapan and Brunhaver, John and Friedman, Joseph S. and Incorvia, Jean Anne C. and Marinella, Matthew J.},
abstractNote = {The domain wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this work, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that, while the energy cost of systems driven by spin-transfer torque (STT) domain wall motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS sub-processor component. This result clarifies the path towards practical implementations of an all-magnetic processor system.},
doi = {10.1109/JXCDC.2019.2955016},
journal = {IEEE Journal on Exploratory Solid-State Computational Devices and Circuits},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {11}
}

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