Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder
The domain wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this work, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that, while the energy cost of systems driven by spin-transfer torque (STT) domain wall motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS sub-processor component. This result clarifies the path towards practical implementations of an all-magnetic processor system.
- Research Organization:
- Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Sandia National Laboratories, Livermore, CA
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA)
- Grant/Contract Number:
- AC04-94AL85000; NA0003525
- OSTI ID:
- 1595031
- Alternate ID(s):
- OSTI ID: 1617327
- Report Number(s):
- SAND--2019-14855J; 682344
- Journal Information:
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Journal Name: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Journal Issue: 2 Vol. 5; ISSN 2329-9231
- Country of Publication:
- United States
- Language:
- English
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