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Title: A multi-layer SEU mitigation strategy to improve FPGA design robustness for the ATLAS muon spectrometer upgrade

Abstract

We present a multi-layer single-event upset mitigation strategy implemented in a low-cost Xilinx Artix-7 FPGA. The implementation is targeted for a trigger data router for the ATLAS muon spectrometer upgrade. The mitigation strategy employs three layers of protection to improve overall FPGA design robustness: use of triple-modular redundancy for FPGA fabric logic and embedded soft-error mitigation in the first layer; further enhancement with multi-boot FPGA reconfiguration across multiple copies of configuration memory in the second layer; and FPGA power cycling and configuration memory re-initialization in the third layer. Here, the effectiveness of this scheme has been evaluated at two different neutron facilities, LANSCE and NCSR ‘‘Demokritos’’, with 800 MeV and 25 MeV beam energies, respectively. Testing was performed with a similar configuration to that planned for final operation. We discuss the testing strategy and summarize the test results to estimate the expected data loss over 10 years of operation in the ATLAS experiment.

Authors:
 [1];  [1];  [1];  [2];  [1];  [1]
  1. Univ. of Michigan, Ann Arbor, MI (United States)
  2. Academia Sinica, Taipei (Taiwan)
Publication Date:
Research Org.:
Univ. of Michigan, Ann Arbor, MI (United States)
Sponsoring Org.:
USDOE Office of Science (SC), High Energy Physics (HEP)
OSTI Identifier:
1643338
Alternate Identifier(s):
OSTI ID: 1523546
Grant/Contract Number:  
SC0007859; SC0007857; AC02-98CH10886
Resource Type:
Accepted Manuscript
Journal Name:
Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment
Additional Journal Information:
Journal Volume: 939; Journal Issue: C; Journal ID: ISSN 0168-9002
Publisher:
Elsevier
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; FPGA; Radiation effect; Single-event upsets (SEUs); Radiation hardening; Muon spectrometer; ATLAS

Citation Formats

Hu, Xueye, Wang, Jinhong, Pinkham, Reid, Hou, Suen, Schwarz, Thomas, and Zhou, Bing. A multi-layer SEU mitigation strategy to improve FPGA design robustness for the ATLAS muon spectrometer upgrade. United States: N. p., 2019. Web. doi:10.1016/j.nima.2019.05.045.
Hu, Xueye, Wang, Jinhong, Pinkham, Reid, Hou, Suen, Schwarz, Thomas, & Zhou, Bing. A multi-layer SEU mitigation strategy to improve FPGA design robustness for the ATLAS muon spectrometer upgrade. United States. https://doi.org/10.1016/j.nima.2019.05.045
Hu, Xueye, Wang, Jinhong, Pinkham, Reid, Hou, Suen, Schwarz, Thomas, and Zhou, Bing. Wed . "A multi-layer SEU mitigation strategy to improve FPGA design robustness for the ATLAS muon spectrometer upgrade". United States. https://doi.org/10.1016/j.nima.2019.05.045. https://www.osti.gov/servlets/purl/1643338.
@article{osti_1643338,
title = {A multi-layer SEU mitigation strategy to improve FPGA design robustness for the ATLAS muon spectrometer upgrade},
author = {Hu, Xueye and Wang, Jinhong and Pinkham, Reid and Hou, Suen and Schwarz, Thomas and Zhou, Bing},
abstractNote = {We present a multi-layer single-event upset mitigation strategy implemented in a low-cost Xilinx Artix-7 FPGA. The implementation is targeted for a trigger data router for the ATLAS muon spectrometer upgrade. The mitigation strategy employs three layers of protection to improve overall FPGA design robustness: use of triple-modular redundancy for FPGA fabric logic and embedded soft-error mitigation in the first layer; further enhancement with multi-boot FPGA reconfiguration across multiple copies of configuration memory in the second layer; and FPGA power cycling and configuration memory re-initialization in the third layer. Here, the effectiveness of this scheme has been evaluated at two different neutron facilities, LANSCE and NCSR ‘‘Demokritos’’, with 800 MeV and 25 MeV beam energies, respectively. Testing was performed with a similar configuration to that planned for final operation. We discuss the testing strategy and summarize the test results to estimate the expected data loss over 10 years of operation in the ATLAS experiment.},
doi = {10.1016/j.nima.2019.05.045},
journal = {Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment},
number = C,
volume = 939,
place = {United States},
year = {Wed May 22 00:00:00 EDT 2019},
month = {Wed May 22 00:00:00 EDT 2019}
}

Journal Article:

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Cited by: 6 works
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Figures / Tables:

Fig. 1 Fig. 1: Illustration of signal flow of the primary trigger path in the ATLAS NSW detector and the role of Router in handling the serial streams.

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Works referenced in this record:

FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
journal, October 2015

  • Wang, Jinhong; Hu, Xueye; Schwarz, Thomas
  • IEEE Transactions on Nuclear Science, Vol. 62, Issue 5
  • DOI: 10.1109/TNS.2015.2477089

Fixed-Latency Gigabit Serial Links in a Xilinx FPGA for the Upgrade of the Muon Spectrometer at the ATLAS Experiment
journal, January 2018

  • Wang, Jinhong; Hu, Xueye; Pinkham, Reid
  • IEEE Transactions on Nuclear Science, Vol. 65, Issue 1
  • DOI: 10.1109/TNS.2017.2784411

High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond
journal, March 2015


SRAM based re-programmable FPGA for space applications
journal, January 1999

  • Wang, J. J.; Katz, R. B.; Sun, J. S.
  • IEEE Transactions on Nuclear Science, Vol. 46, Issue 6
  • DOI: 10.1109/23.819146

FPGAs operating in a radiation environment: lessons learned from FPGAs in space
journal, February 2013


A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs
journal, October 2009

  • Quinn, Heather M.; Graham, Paul S.; Wirthlin, Michael J.
  • IEEE Transactions on Instrumentation and Measurement, Vol. 58, Issue 10
  • DOI: 10.1109/TIM.2009.2025469

A Hybrid Approach to FPGA Configuration Scrubbing
journal, January 2017

  • Stoddard, Aaron; Gruwell, Ammon; Zabriskie, Peter
  • IEEE Transactions on Nuclear Science, Vol. 64, Issue 1
  • DOI: 10.1109/TNS.2016.2636666

An Analysis of High-Current Events Observed on Xilinx 7-Series and Ultrascale Field-Programmable Gate Arrays
conference, January 2016

  • Lee, David S.; Swift, Gary; Wirthlin, Michael
  • 2016 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2016), 2016 IEEE Radiation Effects Data Workshop (REDW)
  • DOI: 10.1109/NSREC.2016.7891703

Single-Event Characterization of the 28 nm Xilinx Kintex-7 Field-Programmable Gate Array under Heavy Ion Irradiation
conference, July 2014

  • Lee, David S.; Wirthlin, Michael; Swift, Gary
  • 2014 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with NSREC 2014)
  • DOI: 10.1109/REDW.2014.7004595

Evaluating Xilinx 7 Series GTX Transceivers for Use in High Energy Physics Experiments Through Proton Irradiation
journal, December 2015

  • Cannon, Matthew; Wirthlin, Michael; Camplani, Alessandra
  • IEEE Transactions on Nuclear Science, Vol. 62, Issue 6
  • DOI: 10.1109/TNS.2015.2497216

ATLAS Muon Drift Tube Electronics
journal, September 2008


The Use of Triple-Modular Redundancy to Improve Computer Reliability
journal, April 1962

  • Lyons, R. E.; Vanderkulk, W.
  • IBM Journal of Research and Development, Vol. 6, Issue 2
  • DOI: 10.1147/rd.62.0200

SEE Measurements and Simulations Using Mono-Energetic GeV-Energy Hadron Beams
journal, December 2013

  • Alia, Ruben Garcia; Brugger, Markus; Danzeca, Salvatore
  • IEEE Transactions on Nuclear Science, Vol. 60, Issue 6
  • DOI: 10.1109/TNS.2013.2279690

Works referencing / citing this record:

Radiation tolerance of online trigger system for COMET Phase-I
text, January 2020