Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs

Menk, Lyle Alexander; Baca, Ehren; Blain, Matthew G.; McClain, Jaime L.; Dominguez, Jason James; Smith, Anna; Hollowell, Andrew E.

doi:10.1149/2.0271901jes

Title: Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs

Abstract

A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.

Authors:

^[1]; Baca, Ehren ^[1]; Blain, Matthew G. ^[1]; McClain, Jaime L. ^[1]; Dominguez, Jason James ^[1]; Smith, Anna ^[1];

^[1]

Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Publication Date:: Thu Dec 13 00:00:00 EST 2018

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: USDOE National Nuclear Security Administration (NNSA)

OSTI Identifier:: 1492855

Report Number(s):: SAND-2018-9018J
Journal ID: ISSN 0013-4651; 667176

Grant/Contract Number:: AC04-94AL85000

Resource Type:: Accepted Manuscript

Journal Name:: Journal of the Electrochemical Society

Additional Journal Information:: Journal Volume: 166; Journal Issue: 1; Journal ID: ISSN 0013-4651

Publisher:: The Electrochemical Society

Country of Publication:: United States

Language:: English

Subject:: 37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CHEMISTRY; Electrodeposition - Copper; MEMs; Microelectronics - Semiconductor Processing; 3D Interconnects; Through Silicon Vias; TSV

Citation Formats


                    Menk, Lyle Alexander, Baca, Ehren, Blain, Matthew G., McClain, Jaime L., Dominguez, Jason James, Smith, Anna, and Hollowell, Andrew E. Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs.  United States: N. p., 2018. 
Web.  doi:10.1149/2.0271901jes.

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                    Menk, Lyle Alexander, Baca, Ehren, Blain, Matthew G., McClain, Jaime L., Dominguez, Jason James, Smith, Anna, & Hollowell, Andrew E. Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs.  United States.  https://doi.org/10.1149/2.0271901jes

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                    Menk, Lyle Alexander, Baca, Ehren, Blain, Matthew G., McClain, Jaime L., Dominguez, Jason James, Smith, Anna, and Hollowell, Andrew E. Thu .  
"Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs".  United States.  https://doi.org/10.1149/2.0271901jes.  https://www.osti.gov/servlets/purl/1492855.

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@article{osti_1492855,

  title        = {Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs},

  author       = {Menk, Lyle Alexander and Baca, Ehren and Blain, Matthew G. and McClain, Jaime L. and Dominguez, Jason James and Smith, Anna and Hollowell, Andrew E.},

  abstractNote = {A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.},

  doi          = {10.1149/2.0271901jes},

  journal      = {Journal of the Electrochemical Society},

  number       = 1,

  volume       = 166,

  place        = {United States},

  year         = {Thu Dec 13 00:00:00 EST 2018},

  month        = {Thu Dec 13 00:00:00 EST 2018}

}

Copy to clipboard

Journal Article:

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https://doi.org/10.1149/2.0271901jes

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Cited by: 13 works

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Figures / Tables:

Figure 1: (a) Graphical illustration of TSV integration approach. (b) Cross-sectional optical image of an array of Cu filled TSVs. (c) Scanning electron micrograph (SEM) of the isolation trench and W vias in the device layer Si of the SOI substrate contacting a two metal layer test structure device. (d)more »

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Works referenced in this record:

High frequency characterization and analytical modeling of through glass via (TGV) for 3D thin-film interposer and MEMS packaging
conference, May 2013

Kim, Cheolbok; Yoon, Yong-Kyu
2013 IEEE 63rd Electronic Components and Technology Conference (ECTC)
DOI: 10.1109/ECTC.2013.6575754

Leveler Effect and Oscillatory Behavior during Copper Electroplating
journal, January 2012

Huang, Q.; Baker-O’Neal, B. C.; Parks, C.
Journal of The Electrochemical Society, Vol. 159, Issue 9
DOI: 10.1149/2.020209jes

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias
journal, January 2013

Wheeler, D.; Moffat, T. P.; Josell, D.
Journal of The Electrochemical Society, Vol. 160, Issue 12
DOI: 10.1149/2.040312jes

Copper electrodeposition for 3D integration
conference, April 2008

Beica, Rozalia; Sharbono, Charles; Ritzdorf, Tom
2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (MEMS/MOEMS)
DOI: 10.1109/dtip.2008.4752967

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing
journal, November 2007

Moffat, T. P.; Wheeler, D.; Kim, S. -K.
Electrochimica Acta, Vol. 53, Issue 1
DOI: 10.1016/j.electacta.2007.03.025

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking
journal, January 2003

Sun, Jian-Jun; Kondo, Kazuo; Okamura, Takuji
Journal of The Electrochemical Society, Vol. 150, Issue 6
DOI: 10.1149/1.1572154

Through-Silicon Via (TSV)
journal, January 2009

Motoyoshi, Makoto
Proceedings of the IEEE, Vol. 97, Issue 1
DOI: 10.1109/jproc.2008.2007462

Superconformal Bottom-Up Nickel Deposition in High Aspect Ratio Through Silicon Vias
journal, January 2016

Josell, D.; Moffat, T. P.
Journal of The Electrochemical Society, Vol. 163, Issue 7
DOI: 10.1149/2.1151607jes

Extreme Bottom-up Filling of Through Silicon Vias and Damascene Trenches with Gold in a Sulfite Electrolyte
journal, January 2013

Josell, D.; Moffat, T. P.
Journal of The Electrochemical Society, Vol. 160, Issue 12
DOI: 10.1149/2.007312jes

Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates
journal, December 2002

Chow, E. M.; Chandrasekaran, V.; Partridge, A.
Journal of Microelectromechanical Systems, Vol. 11, Issue 6
DOI: 10.1109/JMEMS.2002.805206

Modeling Extreme Bottom-Up Filling of Through Silicon Vias
journal, January 2012

Josell, D.; Wheeler, D.; Moffat, T. P.
Journal of The Electrochemical Society, Vol. 159, Issue 10
DOI: 10.1149/2.009210jes

High aspect ratio TSV copper filling with different seed layers
conference, May 2008

Wolf, M. Jurgen; Dretschkow, Thomas; Wunderle, Bernhard
2008 58th Electronic Components and Technology Conference (ECTC 2008)
DOI: 10.1109/ECTC.2008.4550029

Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging
journal, June 2013

Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki
Journal of Micromechanics and Microengineering, Vol. 23, Issue 8
DOI: 10.1088/0960-1317/23/8/085012

Process integration and challenges of Through Silicon Via (TSV) on silicon-on insulator (SOI) substrate for 3D heterogeneous applications
conference, December 2015

Lau, Guan-Kian; Soon, Jeffrey; Li, Hong-Yu
2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)
DOI: 10.1109/EPTC.2015.7412340

Double-Sided Process for MEMS SOI Sensors With Deep Vertical Thru-Wafer Interconnects
journal, April 2018

Efimovskaya, Alexandra; Lin, Yu-Wei; Shkel, Andrei M.
Journal of Microelectromechanical Systems, Vol. 27, Issue 2
DOI: 10.1109/JMEMS.2017.2786663

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology
journal, November 2018

Menk, L. A.; Josell, D.; Moffat, T. P.
Journal of The Electrochemical Society, Vol. 166, Issue 1
DOI: 10.1149/2.0091901jes

Through silicon via technology — processes and reliability for wafer-level 3D system integration
conference, May 2008

Ramm, P.; Wolf, M. J.; Klumpp, A.
2008 58th Electronic Components and Technology Conference (ECTC 2008)
DOI: 10.1109/ECTC.2008.4550074

Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns
journal, January 2012

Moffat, T. P.; Josell, D.
Journal of The Electrochemical Society, Vol. 159, Issue 4
DOI: 10.1149/2.040204jes

3D integration review
journal, May 2011

Farooq, Mukta G.; Iyer, Subramanian S.
Science China Information Sciences, Vol. 54, Issue 5
DOI: 10.1007/s11432-011-4226-7

Superconformal Copper Deposition in Through Silicon Vias by Suppression-Breakdown
journal, January 2018

Josell, D.; Moffat, T. P.
Journal of The Electrochemical Society, Vol. 165, Issue 2
DOI: 10.1149/2.0061802jes

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing
text, January 2014

Wheeler, Daniel; Kim, S. -K
figshare
DOI: 10.6084/m9.figshare.1041793.v1

Bottom-up filling optimization for efficient TSV metallization
journal, March 2010

Delbos, Elise; Omnès, Laurent; Etcheberry, Arnaud
Microelectronic Engineering, Vol. 87, Issue 3
DOI: 10.1016/j.mee.2009.06.008

Wafer-level bonding/stacking technology for 3D integration
journal, April 2010

Ko, Cheng-Ta; Chen, Kuan-Neng
Microelectronics Reliability, Vol. 50, Issue 4
DOI: 10.1016/j.microrel.2009.09.015

Changing Superfilling Mode for Copper Electrodeposition in Blind Holes from Differential Inhibition to Differential Acceleration
journal, January 2009

Lühn, O.; Radisic, A.; Vereecken, P. M.
Electrochemical and Solid-State Letters, Vol. 12, Issue 5
DOI: 10.1149/1.3087790

MSA as a Supporting Electrolyte in Copper Electroplating for Filling of Damascene Trenches and Through Silicon Vias
journal, January 2011

Ki Cho, Sung; Jun Kim, Myung; Jeong Kim, Jae
Electrochemical and Solid-State Letters, Vol. 14, Issue 5
DOI: 10.1149/1.3557758

Superconformal Bottom-up Nickel Deposition in High Aspect Ratio through Silicon Vias
journal, August 2016

Josell, D.; Moffat, T. P.
ECS Transactions, Vol. 75, Issue 2
DOI: 10.1149/07502.0019ecst

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing
text, January 2014

Wheeler, Daniel; Kim, S. -K
figshare
DOI: 10.6084/m9.figshare.1041793

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias
text, January 2014

Wheeler, Daniel
figshare
DOI: 10.6084/m9.figshare.1041795

High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking
journal, January 2005

Kondo, Kazuo; Yonezawa, Toshihiro; Mikami, Daisuke
Journal of The Electrochemical Society, Vol. 152, Issue 11
DOI: 10.1149/1.2041047

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias
text, January 2014

Wheeler, Daniel
figshare
DOI: 10.6084/m9.figshare.1041795.v1

Copper Electrodeposition for 3D Integration
text, January 2008

Beica, Rozalia; Sharbono, Charles; Ritzdorf, Tom
arXiv
DOI: 10.48550/arxiv.0805.0916

Works referencing / citing this record:

Bromide Ion as a Leveler for High-Speed TSV Filling
journal, January 2019

Sung, Minjae; Yoon, Young; Hong, Jinwoo
Journal of The Electrochemical Society, Vol. 166, Issue 13
DOI: 10.1149/2.0181913jes

Inhibition Effect of CTAB on Electrodeposition of Cu in Micro Via: Experimental and MD Simulation Investigations
journal, January 2019

Wu, Houya; Li, Zhiyi; Wang, Yan
Journal of The Electrochemical Society, Vol. 166, Issue 15
DOI: 10.1149/2.0651915jes

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology
journal, November 2018

Menk, L. A.; Josell, D.; Moffat, T. P.
Journal of The Electrochemical Society, Vol. 166, Issue 1
DOI: 10.1149/2.0091901jes

Figures / Tables found in this record:

Figures/Tables have been extracted from DOE-funded journal article accepted manuscripts.

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Similar Records

Title: Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs

Abstract

Citation Formats

Figures / Tables:

High frequency characterization and analytical modeling of through glass via (TGV) for 3D thin-film interposer and MEMS packaging conference, May 2013

Leveler Effect and Oscillatory Behavior during Copper Electroplating journal, January 2012

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias journal, January 2013

Copper electrodeposition for 3D integration conference, April 2008

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing journal, November 2007

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking journal, January 2003

Through-Silicon Via (TSV) journal, January 2009

Superconformal Bottom-Up Nickel Deposition in High Aspect Ratio Through Silicon Vias journal, January 2016

Extreme Bottom-up Filling of Through Silicon Vias and Damascene Trenches with Gold in a Sulfite Electrolyte journal, January 2013

Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates journal, December 2002

Modeling Extreme Bottom-Up Filling of Through Silicon Vias journal, January 2012

High aspect ratio TSV copper filling with different seed layers conference, May 2008

Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging journal, June 2013

Process integration and challenges of Through Silicon Via (TSV) on silicon-on insulator (SOI) substrate for 3D heterogeneous applications conference, December 2015

Double-Sided Process for MEMS SOI Sensors With Deep Vertical Thru-Wafer Interconnects journal, April 2018

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology journal, November 2018

Through silicon via technology — processes and reliability for wafer-level 3D system integration conference, May 2008

Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns journal, January 2012

3D integration review journal, May 2011

Superconformal Copper Deposition in Through Silicon Vias by Suppression-Breakdown journal, January 2018

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing text, January 2014

Bottom-up filling optimization for efficient TSV metallization journal, March 2010

Wafer-level bonding/stacking technology for 3D integration journal, April 2010

Changing Superfilling Mode for Copper Electrodeposition in Blind Holes from Differential Inhibition to Differential Acceleration journal, January 2009

MSA as a Supporting Electrolyte in Copper Electroplating for Filling of Damascene Trenches and Through Silicon Vias journal, January 2011

Superconformal Bottom-up Nickel Deposition in High Aspect Ratio through Silicon Vias journal, August 2016

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing text, January 2014

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias text, January 2014

High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking journal, January 2005

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias text, January 2014

Copper Electrodeposition for 3D Integration text, January 2008

Bromide Ion as a Leveler for High-Speed TSV Filling journal, January 2019

Inhibition Effect of CTAB on Electrodeposition of Cu in Micro Via: Experimental and MD Simulation Investigations journal, January 2019

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology journal, November 2018

High frequency characterization and analytical modeling of through glass via (TGV) for 3D thin-film interposer and MEMS packaging
conference, May 2013

Leveler Effect and Oscillatory Behavior during Copper Electroplating
journal, January 2012

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias
journal, January 2013

Copper electrodeposition for 3D integration
conference, April 2008

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing
journal, November 2007

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking
journal, January 2003

Through-Silicon Via (TSV)
journal, January 2009

Superconformal Bottom-Up Nickel Deposition in High Aspect Ratio Through Silicon Vias
journal, January 2016

Extreme Bottom-up Filling of Through Silicon Vias and Damascene Trenches with Gold in a Sulfite Electrolyte
journal, January 2013

Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates
journal, December 2002

Modeling Extreme Bottom-Up Filling of Through Silicon Vias
journal, January 2012

High aspect ratio TSV copper filling with different seed layers
conference, May 2008

Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging
journal, June 2013

Process integration and challenges of Through Silicon Via (TSV) on silicon-on insulator (SOI) substrate for 3D heterogeneous applications
conference, December 2015

Double-Sided Process for MEMS SOI Sensors With Deep Vertical Thru-Wafer Interconnects
journal, April 2018

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology
journal, November 2018

Through silicon via technology — processes and reliability for wafer-level 3D system integration
conference, May 2008

Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns
journal, January 2012

3D integration review
journal, May 2011

Superconformal Copper Deposition in Through Silicon Vias by Suppression-Breakdown
journal, January 2018

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing
text, January 2014

Bottom-up filling optimization for efficient TSV metallization
journal, March 2010

Wafer-level bonding/stacking technology for 3D integration
journal, April 2010

Changing Superfilling Mode for Copper Electrodeposition in Blind Holes from Differential Inhibition to Differential Acceleration
journal, January 2009

MSA as a Supporting Electrolyte in Copper Electroplating for Filling of Damascene Trenches and Through Silicon Vias
journal, January 2011

Superconformal Bottom-up Nickel Deposition in High Aspect Ratio through Silicon Vias
journal, August 2016

Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing
text, January 2014

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias
text, January 2014

High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking
journal, January 2005

Spatial-Temporal Modeling of Extreme Bottom-up Filling of Through-Silicon-Vias
text, January 2014

Copper Electrodeposition for 3D Integration
text, January 2008

Bromide Ion as a Leveler for High-Speed TSV Filling
journal, January 2019

Inhibition Effect of CTAB on Electrodeposition of Cu in Micro Via: Experimental and MD Simulation Investigations
journal, January 2019

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology
journal, November 2018