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Title: Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs

Abstract

A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.

Authors:
ORCiD logo [1];  [1];  [1];  [1];  [1];  [1]; ORCiD logo [1]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1492855
Report Number(s):
SAND-2018-9018J
Journal ID: ISSN 0013-4651; 667176
Grant/Contract Number:  
AC04-94AL85000
Resource Type:
Accepted Manuscript
Journal Name:
Journal of the Electrochemical Society
Additional Journal Information:
Journal Volume: 166; Journal Issue: 1; Journal ID: ISSN 0013-4651
Publisher:
The Electrochemical Society
Country of Publication:
United States
Language:
English
Subject:
37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CHEMISTRY; Electrodeposition - Copper; MEMs; Microelectronics - Semiconductor Processing; 3D Interconnects; Through Silicon Vias; TSV

Citation Formats

Menk, Lyle Alexander, Baca, Ehren, Blain, Matthew G., McClain, Jaime L., Dominguez, Jason James, Smith, Anna, and Hollowell, Andrew E. Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs. United States: N. p., 2018. Web. doi:10.1149/2.0271901jes.
Menk, Lyle Alexander, Baca, Ehren, Blain, Matthew G., McClain, Jaime L., Dominguez, Jason James, Smith, Anna, & Hollowell, Andrew E. Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs. United States. doi:10.1149/2.0271901jes.
Menk, Lyle Alexander, Baca, Ehren, Blain, Matthew G., McClain, Jaime L., Dominguez, Jason James, Smith, Anna, and Hollowell, Andrew E. Thu . "Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs". United States. doi:10.1149/2.0271901jes. https://www.osti.gov/servlets/purl/1492855.
@article{osti_1492855,
title = {Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs},
author = {Menk, Lyle Alexander and Baca, Ehren and Blain, Matthew G. and McClain, Jaime L. and Dominguez, Jason James and Smith, Anna and Hollowell, Andrew E.},
abstractNote = {A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.},
doi = {10.1149/2.0271901jes},
journal = {Journal of the Electrochemical Society},
number = 1,
volume = 166,
place = {United States},
year = {2018},
month = {12}
}

Journal Article:
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Cited by: 1 work
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Figures / Tables:

Figure 1 Figure 1: (a) Graphical illustration of TSV integration approach. (b) Cross-sectional optical image of an array of Cu filled TSVs. (c) Scanning electron micrograph (SEM) of the isolation trench and W vias in the device layer Si of the SOI substrate contacting a two metal layer test structure device. (d)more » SEM of W vias implanted in device layer Si making electrical contact to ECD Cu. (e) SEM of Cu filled TSV at the top side of an SOI substrate.« less

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