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Title: A 65 nm CMOS analog processor with zero dead time for future pixel detectors

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm –2 s –1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. In conclusion, a thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.
Authors:
 [1] ;  [2] ;  [2] ;  [2] ;  [2] ;  [3] ;  [4] ;  [1] ;  [2]
  1. Univ. di Bergamo, Dalmine (Italy); INFN, Pavia (Italy)
  2. Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
  3. Univ. di Bergamo, Dalmine (Italy); INFN, Pavia (Italy); Centre National de Recherche Scientifique, Paris (France)
  4. Univ. di Pavia, Pavia (Italy); INFN, Pavia (Italy)
Publication Date:
Report Number(s):
FERMILAB-CONF-16-776-PPD
Journal ID: ISSN 0168-9002; 1513605
Grant/Contract Number:
AC02-07CH11359
Type:
Accepted Manuscript
Journal Name:
Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment
Additional Journal Information:
Journal Volume: 845; Journal Issue: C; Journal ID: ISSN 0168-9002
Publisher:
Elsevier
Research Org:
Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
Sponsoring Org:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; Pixel detectors; Analog front-end; CMOS; Zero dead time processor; High-Luminosity LHC
OSTI Identifier:
1471562

Gaioni, Luigi, Braga, D., Christian, D. C., Deptuch, G., Fahim, F., Nodari, B., Ratti, L., Re, V., and Zimmerman, T.. A 65 nm CMOS analog processor with zero dead time for future pixel detectors. United States: N. p., Web. doi:10.1016/j.nima.2016.04.053.
Gaioni, Luigi, Braga, D., Christian, D. C., Deptuch, G., Fahim, F., Nodari, B., Ratti, L., Re, V., & Zimmerman, T.. A 65 nm CMOS analog processor with zero dead time for future pixel detectors. United States. doi:10.1016/j.nima.2016.04.053.
Gaioni, Luigi, Braga, D., Christian, D. C., Deptuch, G., Fahim, F., Nodari, B., Ratti, L., Re, V., and Zimmerman, T.. 2016. "A 65 nm CMOS analog processor with zero dead time for future pixel detectors". United States. doi:10.1016/j.nima.2016.04.053. https://www.osti.gov/servlets/purl/1471562.
@article{osti_1471562,
title = {A 65 nm CMOS analog processor with zero dead time for future pixel detectors},
author = {Gaioni, Luigi and Braga, D. and Christian, D. C. and Deptuch, G. and Fahim, F. and Nodari, B. and Ratti, L. and Re, V. and Zimmerman, T.},
abstractNote = {Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×1034 cm–2 s–1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. In conclusion, a thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.},
doi = {10.1016/j.nima.2016.04.053},
journal = {Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment},
number = C,
volume = 845,
place = {United States},
year = {2016},
month = {4}
}