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Title: Extending Moore's Law via Computationally Error Tolerant Computing.

Dennard scaling has ended. Lowering the voltage supply (V dd) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower V dd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower V dd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. Finally, from the simulation results, this RRNS system can reduce the energy-delay-product by about 3× for multiplication intensive workloads and by about 2× in general, when compared to a non-error-correcting binary core.
Authors:
 [1] ;  [1] ;  [1] ;  [1] ;  [2] ;  [2] ;  [2]
  1. Georgia Inst. of Technology, Atlanta, GA (United States)
  2. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
Report Number(s):
SAND-2018-0257J
Journal ID: ISSN 1544-3566; 659857
Grant/Contract Number:
AC04-94AL85000
Type:
Accepted Manuscript
Journal Name:
ACM Transactions on Architecture and Code Optimization
Additional Journal Information:
Journal Volume: 15; Journal Issue: 1; Journal ID: ISSN 1544-3566
Publisher:
Association for Computing Machinery
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE National Nuclear Security Administration (NNSA)
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING
OSTI Identifier:
1432788

Deng, Bobin, Srikanth, Sriseshan, Hein, Eric R., Conte, Thomas M., Debenedictis, Erik, Cook, Jeanine, and Frank, Michael. Extending Moore's Law via Computationally Error Tolerant Computing.. United States: N. p., Web. doi:10.1145/3177837.
Deng, Bobin, Srikanth, Sriseshan, Hein, Eric R., Conte, Thomas M., Debenedictis, Erik, Cook, Jeanine, & Frank, Michael. Extending Moore's Law via Computationally Error Tolerant Computing.. United States. doi:10.1145/3177837.
Deng, Bobin, Srikanth, Sriseshan, Hein, Eric R., Conte, Thomas M., Debenedictis, Erik, Cook, Jeanine, and Frank, Michael. 2018. "Extending Moore's Law via Computationally Error Tolerant Computing.". United States. doi:10.1145/3177837.
@article{osti_1432788,
title = {Extending Moore's Law via Computationally Error Tolerant Computing.},
author = {Deng, Bobin and Srikanth, Sriseshan and Hein, Eric R. and Conte, Thomas M. and Debenedictis, Erik and Cook, Jeanine and Frank, Michael},
abstractNote = {Dennard scaling has ended. Lowering the voltage supply (Vdd) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower Vdd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower Vdd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. Finally, from the simulation results, this RRNS system can reduce the energy-delay-product by about 3× for multiplication intensive workloads and by about 2× in general, when compared to a non-error-correcting binary core.},
doi = {10.1145/3177837},
journal = {ACM Transactions on Architecture and Code Optimization},
number = 1,
volume = 15,
place = {United States},
year = {2018},
month = {3}
}

Works referenced in this record:

Self-checked computation using residue arithmetic
journal, January 1966
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  • Proceedings of the IEEE, Vol. 54, Issue 12, p. 1920-1931
  • DOI: 10.1109/PROC.1966.5275

In Quest of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor
journal, December 2010